Electrostatic discharge protection circuit
The present invention discloses an electrostatic discharge protection circuit, comprising a diode and a N-type metal-oxide-semiconductor (NMOS) transistor. The diode locating on a N-well comprises an high P-doping concentration region and an nonadjacent high N-doping concentration region. The NMOS transistor, locating on a P-well, comprises a drain, a source and a gate, and the drain and the source are formed by the high N-doping concentration region. Wherein the P-well further comprises a high P-doping concentration region near the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, the gate of the NMOS transistor electrically connected to a trigger point. Accordingly, the electrostatic discharge protection circuit has a low parasitic capacitance, wide operating voltage range and high electrostatic discharge (ESD) capability for resolving the problems about the ESD of the RX pins.
1. An electrostatic discharge protection circuit, formed by a diode and a metal-oxide-semiconductor (MOS) transistor set on a semiconducting substrate, comprising:
a first well, having a first conducting mode;
a second well, locating adjacent to the first well and having a second conducting mode;
a first high doping concentration region, locating in the second well and having a second conducting mode, the first high doping concentration region electrically connected to a connected pad;
a second high doping concentration region, locating in the second well and having a first predetermined distance from the first high doping concentration region, having a first conducting mode;
a third high doping concentration region, locating in the second well and having a first conducting mode;
a fourth high doping concentration region, locating in the first well and having a second predetermined distance from the third high doping concentration region, having a first conducting mode, the fourth high doping concentration region electrically connected to a ground pad;
a fifth high doping concentration region, locating in the first well and locating adjacent to the fourth high doping concentration region, having a second conducting mode, the fifth high doping concentration region electrically connected to the ground pad; and an electrode, locating on a surface of the second well between the third high doping concentration region and the fourth high doping concentration region, the electrode electrically connected to a trigger point;
wherein the second high doping concentration region is electrically connected to the third high doping concentration region.
2. An electrostatic discharge protection circuit as claimed in claim 1 , wherein the first conducting mode is N-type, the second conducting mode is P-type.
3. An electrostatic discharge protection circuit as claimed in claim 1 , wherein a parasitic effect between the first high doping concentration region, the first well and the second well forms a first bipolar transistor, the first high doping concentration region forms as a collector of the first bipolar transistor, the first well forms as a base of the first bipolar transistor, and the second well forms as an emitter of the first bipolar transistor.
4. An electrostatic discharge protection circuit as claimed in claim 1 , wherein a parasitic effect between the fourth high doping concentration region, the first well and the second well forms a second bipolar transistor, the fourth high doping concentration region forms as a collector of the second bipolar transistor, the second well forms as a base of the second bipolar transistor, the first well forms as an emitter of the second bipolar transistor.
5. An electrostatic discharge protection circuit as claimed in claim 1 , wherein a parasitic effect between the first high doping concentration region, the fourth high doping concentration region, the first well and the second well parasitically forms a silicon controlled rectifier (SCR).
6. An electrostatic discharge protection circuit as claimed in claim 1 , wherein a first parasitic effect between the first high doping concentration region, the first well and the second well forms a first bipolar transistor, the second well forms as a base of the first bipolar transistor, a second parasitic effect between the fourth high doping concentration region, the first well and the second well forms a second bipolar transistor, the first well forms as a base of the second bipolar transistor, and the first bipolar transistor and the second bipolar transistor form as a silicon controlled rectifier (SCR).
7. An electrostatic discharge protection circuit as claimed in claim 1 , wherein an isolating layer having a thickness is located between the electrode and the surface of the first well.
8. An electrostatic discharge protection circuit as claimed in claim 1 , wherein the third high doping concentration region, the fourth high doping concentration region and the electrode forms as a metal-oxide-semiconductor (MOS) field-effect transistor (FET), the electrode formed as a gate of the FET.
9. An electrostatic discharge protection circuit as claimed in claim 1 , wherein the fifth high doping concentration region is located closer to the junction of the first well and the second well than the fourth high doping concentration region, and the fifth high doping concentration region is used to adjust a trigger voltage of the trigger point.
10. An electrostatic discharge protection circuit as claimed in claim 1 , wherein the second high doping concentration region and the third high doping concentration region electrically connect to a point with high voltage.
11. An electrostatic discharge protection circuit, comprising:
a diode, locating on a N-well, including a high P-doping concentration region and a nonadjacent high N-doping concentration region;
a N-type metal-oxide-semiconductor (NMOS) transistor, locating on a P-well, including a drain, a source and a gate, the drain and the source formed by the high N-doping concentration region;
wherein the P-well further comprises a high P-doping concentration region adjacent to the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, the gate of the NMOS transistor electrically connected to a trigger point.
12. An electrostatic discharge protection circuit as claimed in claim 11 , wherein the drain of the NMOS transistor and the high N-doping concentration region of the diode are electrically connected to a point with high voltage.
13. An electrostatic discharge protection circuit as claimed in claim 11 , wherein a parasitic effect between the high P-doping concentration region of the diode, the N-well, the P-well and the source of the NMOS transistor forms a silicon controlled rectifier (SCR).
14. An electrostatic discharge protection circuit as claimed in claim 11 , wherein a first parasitic effect between the high P-doping concentration region of the diode, the N-well and the P-well forms a first bipolar transistor, the N-well forms as a base of the first bipolar transistor, a second parasitic effect between the source of the NMOS transistor, the N-well and the P-well forms a second bipolar transistor, the P-well forms as a base of the second bipolar transistor, the first bipolar transistor and the second bipolar transistor form as a silicon controlled rectifier (SCR).