Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion
A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.
1. A semiconductor device comprising:
a shallow trench isolation formed in a semiconductor substrate, the shallow trench isolation comprising a first oxide formed in a lower portion of a trench of the shallow trench isolation and a second oxide formed in an upper portion of the trench and above a surface of the first oxide; and
a portion of the semiconductor device completely traversing the trench, the portion being formed over and contacting a portion of an essentially planar top surface of the second oxide that extends from adjacent to a first side of the trench to adjacent to a second side of the trench opposite the first side.
2. The semiconductor device of claim 1 , wherein an oxygen concentration of the second oxide is lower than an oxygen concentration of the first oxide.
3. The semiconductor device of claim 1 , wherein an oxygen concentration of the second oxide is approximately the same as an oxygen concentration of the first oxide.
4. The semiconductor device of claim 1 , wherein the portion of the semiconductor device comprises a high dielectric constant metal gate.
5. The semiconductor device of claim 4 , wherein the high dielectric constant metal gate completely traverses the trench and regions of the semiconductor substrate on opposite sides of the trench.
6. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises one of a silicon-on-insulator substrate and a bulk silicon substrate.
7. A semiconductor device comprising:
a shallow trench isolation formed in a semiconductor substrate, the shallow trench isolation comprising a first oxide formed in a lower portion of a trench of the shallow trench isolation and a second oxide formed in an upper portion of the trench and above a surface of the first oxide; and
a portion of the semiconductor device formed over and contacting at least a portion of a surface of the second oxide, wherein an oxygen concentration of the second oxide is lower than an oxygen concentration of the first oxide.
8. The semiconductor device of claim 7 , further comprising a liner at least partially conforming to interior surfaces of the lower portion of the trench, wherein the liner at least partially encases sides of the first oxide, wherein the second oxide is formed over and in contact with a part of the surface of the first oxide, over top surfaces of the liner, and to contact interior surfaces of the upper portion of the trench.
9. The semiconductor device of claim 8 , wherein the liner comprises a high-k material.
10. The semiconductor device of claim 8 , wherein the liner comprises at least one of an oxygen sink or an oxygen barrier.
11. The semiconductor device of claim 10 , wherein the liner comprises at least one of HfO 2 , HfSiO 4 , or SiN.
12. The semiconductor device of claim 7 , wherein the portion of the semiconductor device comprises a high dielectric constant metal gate that completely traverses the trench.
13. The semiconductor device of claim 12 , wherein the high dielectric constant metal gate further completely traverses regions of the semiconductor substrate on opposite sides of the trench.
14. A semiconductor device comprising:
a shallow trench isolation formed in a semiconductor substrate, the shallow trench isolation comprising a first oxide formed in a lower portion of a trench of the shallow trench isolation and a second oxide formed in an upper portion of the trench and above a surface of the first oxide;
a portion of the semiconductor device formed over and contacting at least a portion of a surface of the second oxide; and,
a liner at least partially conforming to and contacting interior surfaces of the upper portion of the trench and conforming to and contacting an upper surface of the first oxide, wherein the liner at least partially encases sides of the second oxide, and wherein the portion of the semiconductor device is formed over and contacts top surfaces of the liner in addition to the at least the portion of the surface of the second oxide.
15. The semiconductor device of claim 14 , wherein an oxygen concentration of the second oxide is lower than an oxygen concentration of the first oxide, and wherein the liner comprises a high-k material.
16. The semiconductor device of claim 14 , wherein the liner comprises at least one of an oxygen sink or an oxygen barrier.
17. The semiconductor device of claim 16 , wherein an oxygen concentration of the second oxide is lower than an oxygen concentration of the first oxide.
18. The semiconductor device of claim 16 , wherein an oxygen concentration of the second oxide is approximately the same as an oxygen concentration of the first oxide.
19. The semiconductor device of claim 16 , wherein the liner comprises at least one of HfO 2 , HfSiO 4 , or SiN.
20. The semiconductor device of claim 14 , wherein the portion of the semiconductor device comprises a high dielectric constant metal gate that completely traverses the trench and further traverses regions of the semiconductor substrate on opposite sides of the trench.