FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same
Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.
1. A fin field-effect transistor device comprising:
a semiconductor substrate having a plurality of fins disposed in parallel relationship;
a first insulator layer overlying the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions;
a gate electrode structure overlying the exposed fin portions and electrically insulated from the fins by a gate insulating layer; and
a first sidewall spacer is disposed adjacent to a first side of the fins and directly over the first insulator layer; and
epitaxially-grown source regions and drain regions disposed adjacent to the gate electrode structure;
wherein the epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins, wherein portions of the epitaxially-grown source regions and drain regions are further disposed overlying a top of the first sidewall spacer and wherein epitaxially-grown source regions and drain regions from adjacent fin field-effect transistors on adjacent fins are isolated from direct physical contact.
2. The fin field-effect transistor device of claim 1 , wherein the epitaxially-grown source regions and drain regions protrude less on a first side of the fins than on a second side of the fins along the lateral direction perpendicular to the length of the fins.
3. The fin field-effect transistor device of claim 2 , free from a second sidewall spacer disposed adjacent to the second side of the fins.
4. The fin field-effect transistor device of claim 3 , wherein the epitaxially-grown source regions and drain regions are further disposed overlying the first sidewall spacer on the first side of the fins and directly on the first insulator layer adjacent to the second side of the fins.
5. The fin field-effect transistor device of claim 1 , wherein a second sidewall spacer is disposed adjacent to a second side of the fins and over the first insulator layer, and wherein the second sidewall spacer is smaller than the first sidewall spacer.
6. The fin field-effect transistor device of claim 5 , wherein portions of the epitaxially-grown source regions and drain regions are further disposed overlying a top of the second sidewall spacer.
7. The fin field-effect transistor device of claim 1 , wherein a second sidewall spacer is disposed adjacent to the second side of the fins and over the first insulator layer, wherein the second sidewall spacer is smaller than the first sidewall spacer, and wherein the epitaxially-grown source regions and drain regions protrude less on the first side of the fins than on a second side of the fins along the lateral direction perpendicular to the length of the fins.
8. The fin field-effect transistor device of claim 1 , wherein the fins are recessed at locations of the epitaxially-grown source regions and drain regions and wherein the epitaxially-grown source regions and drain regions are grown only from the recessed portions of the fins.
9. The fin field-effect transistor device of claim 1 , wherein the fin field-effect transistor device has a single fin transistor configuration.
10. The fin field-effect transistor device of claim 1 , wherein the device is free from a second sidewall spacer disposed adjacent to a second side of the fins, and wherein the epitaxially-grown source regions and drain regions protrude less on the first side of the fins than on a second side of the fins along the lateral direction perpendicular to the length of the fins.