Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base
Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.
1. A device structure for a bipolar junction transistor, the device structure comprising:
an intrinsic base comprised of a first semiconductor material;
an etch stop layer on the intrinsic base, the etch stop layer comprised of a second semiconductor material;
an extrinsic base on the etch stop layer, the extrinsic base comprised of a third semiconductor material;
a first trench penetrating through the extrinsic base and the etch stop layer to the intrinsic base; and
an emitter in the first trench,
wherein the second semiconductor material etches selective to the first semiconductor material and the third semiconductor material.
2. The device structure of claim 1 wherein the intrinsic base includes a first sublayer and a second sublayer between the first sublayer and the etch stop layer, and the first sublayer is comprised of the first semiconductor material, and the second sublayer is comprised of a fourth semiconductor material different from the second semiconductor material of the etch stop layer.
3. The device structure of claim 1 wherein the intrinsic base is formed on a semiconductor substrate, and further comprising:
an isolation region in the semiconductor substrate, the isolation region extending beneath the intrinsic base; and
a collector in the semiconductor substrate, the collector being coextensive with the isolation region.
4. The device structure of claim 3 wherein the isolation region is an air gap, the second semiconductor material comprises silicon—germanium, and the third semiconductor material comprises silicon.
5. The device structure of claim 1 wherein the emitter includes a head that protrudes out of the first trench, and further comprising:
a protective layer at a sidewall of the head of the emitter.
6. The device structure of claim 5 wherein the protective layer comprises a doped region in the sidewall of the head of the emitter and having an opposite conductivity type from a bulk of the emitter.
7. The device structure of claim 5 wherein the protective layer comprises a dielectric spacer on the sidewall of the head of the emitter.
8. The device structure of claim 1 wherein the intrinsic base, the etch stop layer, and the extrinsic base have respective crystal structures with an epitaxial relationship.