Programmable logic unit
Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.
1. An apparatus comprising:
one or more input interfaces;
logic elements;
one or more output interfaces;
a clock selector operable to select a clock signal from two or more clock sources; and
an interconnect array operable to:
distribute the selected clock signal to at least one of the logic elements,
route one or more input signals from the one or more input interfaces to one or more of the logic elements,
route one or more intermediate signals among the logic elements, and route one or more signals from one or more of the logic elements to the one or more output interfaces to produce one or more output signals,
the interconnect array further operable to communicatively couple a logic element programmed as a register with a logic element programmed as a decoder, wherein the logic element programmed as the decoder is operable to decode an input provided by the logic element programmed as the register via the programmable interconnect array, and wherein the logic element programmed as the decoder is operable to produce a decoded output signal as one of the one or more output signals.
2. The apparatus of claim 1 , wherein the clock signal is selected by the clock selector based on whether the apparatus is operating as a master or a slave.
3. The apparatus of claim 1 , wherein at least one clock source is external to the apparatus.
4. The apparatus of claim 1 , wherein the interconnect array is programmable to communicatively couple a logic element programmed as a register with a logic element programmed as an encoder, and wherein the logic element programmed as the encoder is operable to encode an input provided by the logic element programmed as the register via the programmable interconnect array, and wherein the logic element programmed as the encoder is operable to produce an encoded output signal as one of the one or more output signals.
5. The apparatus of claim 1 , wherein at least one of the one or more input or output signals comprises a serial bit-stream.
6. The apparatus of claim 1 , wherein the logic elements comprise:
one or more logic elements that are individually programmable to provide one of a plurality of first functions; and
one or more logic elements that are individually programmable to be one of a plurality of second functions, wherein the plurality of first functions and the plurality of second functions are different by at least one function.
7. A system comprising:
processor unit configured to perform operations; and
a programmable logic unit that is communicatively coupled with the processor unit, the programmable logic unit comprising:
one or more input interfaces to receive one or more input signals;
logic elements;
one or more output interfaces to provide one or more output signals;
an interconnect array operable to form one or more interconnections within the system, route the one or more input signals from the one or more input interfaces to the logic elements, route one or more intermediate signals among the logic elements, route one or more signals from the logic elements to produce the one or more output signals via the one or more output interfaces, distribute a clock signal to at least one of the logic elements, the interconnect array operable to communicatively couple a logic element programmed as a register with a logic element programmed as a decoder, wherein the logic element programmed as the decoder is operable to decode an input provided by the logic element programmed as the register via the programmable interconnect array, and wherein the logic element programmed as the decoder is operable to produce a decoded output signal as one of the one or more output signals; and
a clock selector that is operable to select the clock signal from two or more clock sources.
8. The system of claim 7 , wherein the clock signal is selected by the clock selector based on whether the programmable logic unit is operating as a master or a slave.
9. The system of claim 7 , wherein at least one clock source is external to the programmable logic unit.
10. The system of claim 7 , wherein the interconnect array is programmable to communicatively couple a logic element programmed as a register with a logic element programmed as an encoder, and wherein the logic element programmed as the encoder is operable to encode an input provided by the logic element programmed as the register via the programmable interconnect array, and wherein the logic element programmed as the encoder is operable to produce an encoded output signal as one of the one or more output signals.
11. The system of claim 7 , wherein at least one of the one or more input or output signals comprises a serial bit-stream.
12. The system of claim 7 , wherein the logic elements comprise:
one or more logic elements that are individually programmable to be one of a plurality of first functions; and
one or more logic elements that are individually programmable to be one of a plurality of second functions, wherein the plurality of first functions and the plurality of second functions are different by at least one function.
13. The system of claim 12 , wherein the first functions comprise a truth table, data register, and a buffer register, and wherein the second functions comprise a counter, delay element, and a filter.
14. The system of claim 7 , comprising:
a peripheral that is communicatively coupled with the programmable logic unit; and
an integrated circuit that comprises the processor unit, the programmable logic unit, and the peripheral, wherein the processor unit is operable to program the programmable logic unit to receive at least one of the one or more input signals from the peripheral, provide at least one of the one or more output signals to the peripheral, or both.
15. The system of claim 14 , comprising:
electrical contacts; and
an integrated circuit package that comprises the processor unit, the programmable logic unit, and the electrical contacts, wherein the processor unit is operable to program the programmable logic unit to receive at least one of the one or more input signals from at least a portion of the electrical contacts, provide at least one of the one or more output signals to at least a portion of the electrical contacts, or both.
16. A method comprising:
sending one or more first programming commands to a programmable logic unit to program logic elements of the programmable logic unit, wherein the programmable logic unit includes one or more input interfaces to receive one or more input signals, the logic elements, one or more output interfaces to provide one or more output signals, and a programmable interconnect array, wherein the programmable interconnect array is operable to selectively form one or more interconnections within a group comprising the one or more input interfaces, the one or more output interfaces, and the logic elements;
sending one or more second programming commands to the programmable logic unit to program the programmable interconnect array to route the one or more input signals to at least a portion of the logic elements, route one or more intermediate signals among at least a portion of the logic elements, and route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface;
selecting a clock signal from two or more clock sources; and
distributing the clock signal to at least one of the logic elements.
17. The method of claim 16 , wherein selecting a clock signal further comprises:
determining if the programmable logic unit is being operated as a master or a slave; and
responsive to the determining, selecting the clock signal from a clock source.
18. The method of claim 17 , where the clock source is external to the programmable logic unit.