Substrate structures and methods of manufacture
A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of metallic traces coupled to the electrically insulative layer on a surface of the electrically insulative layer opposing a surface of the electrically insulative layer coupled to the metallic baseplate. The plurality of metallic traces may include at least two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the surface of the electrically insulative layer coupled with the metallic baseplate. The package may include at least one semiconductor device coupled to the substrate, a mold compound that encapsulates the power electronic device and at least a portion of the substrate, and at least one package electrical connector coupled with the substrate.
1. A method of forming a semiconductor package, comprising:
providing an electrically insulative layer having a first surface opposing a second surface;
plating a first copper layer onto the second surface of the electrically insulative layer;
patterning the first copper layer;
forming traces in the first copper layer by etching through exposed portions of the first copper layer;
plating a second copper layer onto the traces in the first copper layer;
patterning the second copper layer;
forming traces in the second copper layer that correspond with the traces in the first copper layer by etching through exposed portions of the second copper layer;
bonding at least one semiconductor device with at least one of the traces in the second copper layer;
encapsulating the at least one semiconductor device with a mold compound; and
bonding at least one package electrical connector with one of the first copper layer and the second copper layer;
wherein a width of the traces of the second copper layer are thinner than a width of the traces of the first copper layer by an offset distance.
2. The method of claim 1 , further comprising:
plating a third copper layer onto the traces in the second copper layer;
patterning the third copper layer;
forming traces in the third copper layer that corresponding with the traces in the second copper layer by etching through exposed portions of the third copper layer;
bonding at least one semiconductor device with at least one of the traces in the third copper layer;
wherein a width of the traces of the third copper layer are thinner than a width of the traces of the second copper layer by an offset distance.
3. The method of claim 1 , wherein the first copper layer and the second copper layer have different thicknesses measured perpendicularly to the second surface of the electrically insulative layer.
4. The method of claim 1 , further comprising:
plating a first copper layer on the first surface of the electrically insulative layer;
patterning the first copper layer;
removing an exposed portion of the first copper layer;
plating a second copper layer onto the first copper layer;
patterning the second copper layer;
removing an exposed portion of the second copper layer;
wherein a distance from an edge of the electrically insulative layer to an edge of the first copper layer is smaller than a distance from the edge of the electrically insulative layer to an edge of the second copper layer.