Selectable programmable gain or operational amplifier
View Patent ↗An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.
1. A configurable amplifier, comprising:
a differential input stage and a bias circuit coupled to the differential input stage;
a first output block;
a second output block;
a feedback network; and
a plurality of switches coupled to the differential input stage, the feedback network, the first output block and the second output block;
wherein
the differential input stage, the feedback network, and the first output block are coupled together as a programmable gain amplifier when certain ones of the plurality of switches are arranged in a first mode,
the differential input stage and the second output block are coupled together as an operational amplifier without any feedback network when the certain ones of the plurality of switches are arranged in a second mode, and
wherein the bias circuit has a first set of bias parameters for the programmable gain amplifier configuration when in the first mode, and a second set of bias parameters for the operational amplifier configuration when in the second mode.
2. The configurable amplifier according to claim 1 , wherein the first output block comprises a first intermediate stage and a first output stage, and the second output block comprises a second intermediate stage and a second output stage.
3. The configurable amplifier according to claim 1 , wherein the first and second bias parameters are stored in a bias memory.
4. The configurable amplifier according to claim 1 , further comprising a calibration circuit coupled to the differential input stage.
5. The configurable amplifier according to claim 3 , wherein the calibration circuit has a first set of calibration parameters for the programmable gain amplifier configuration when in the first mode, and a second set of calibration parameters for the operational amplifier configuration when in the second mode.
6. The configurable amplifier according to claim 4 , wherein the first and second calibration parameters are stored in a calibration memory.
7. The configurable amplifier according to claim 3 , wherein the first and second calibration parameters each have an input offset calibration parameter.
8. The configurable amplifier according to claim 1 , wherein first and second inputs of the differential input stage are coupled to first and second external connections of an integrated circuit when operating in said second mode and only one of the first and second inputs of the differential input stage is coupled to another external connection of an integrated circuit when operating in said first mode.
9. The configurable amplifier according to claim 8 , wherein an output of the first output block is coupled to a third external connection of the integrated circuit.
10. The configurable amplifier according to claim 8 , wherein an output of the second output block is coupled to a fourth external connection of the integrated circuit.
11. The configurable amplifier according to claim 1 , further comprising a mode selection input for selecting between the first mode and the second mode.
12. The configurable amplifier according to claim 1 , further comprising compensation networks for the first and second output blocks.
13. A microcontroller integrated circuit, comprising:
a digital processor and memory;
an analog-to-digital converter (ADC) having a digital output coupled to the digital processor;
a configurable analog amplifier, comprising:
a differential input stage;
a feedback network;
a first output block;
a second output block;
a plurality of switches coupled to the differential input stage, the feedback network, the first output block and the second output block;
and a multiplexer coupled between the first output block and the ADC;
wherein
the differential input stage, the feedback network, and the first output block are coupled together as a programmable gain amplifier when certain ones of the plurality of switches are arranged in a first mode, and
the differential input stage and the second output block are coupled together as an operational amplifier without any feedback network when the certain ones of the plurality of switches are arranged in a second mode; and
the processor controls the first and second modes.
14. A microcontroller integrated circuit, comprising:
a digital processor and memory;
an analog-to-digital converter (ADC) having a digital output coupled to the digital processor;
a configurable analog amplifier, comprising:
a differential input stage;
a feedback network;
a first output block;
a second output block;
a plurality of switches coupled to the differential input stage, the feedback network, the first output block and the second output block;
wherein
the differential input stage, the feedback network, and the first output block are coupled together as a programmable gain amplifier when certain ones of the plurality of switches are arranged in a first mode, and
the differential input stage and the second output block are coupled together as an operational amplifier without any feedback network when the certain ones of the plurality of switches are arranged in a second mode; and
the processor controls the first and second modes; wherein the microcontroller further comprises a configuration register for storing open and close settings of the plurality of switches for the first and second modes.
15. The microcontroller according to claim 14 , further comprising an integrated circuit package having a plurality of external connections thereon.
16. The microcontroller according to claim 15 , wherein first and second inputs of the differential input stage are coupled to first and second ones of the plurality of external connections when operating in said second mode and only one of the first and second inputs of the differential input stage is coupled to another external connection of an integrated circuit when operating in said first mode.
17. The microcontroller according to claim 15 , wherein an output of the first output block is coupled to a third one of the plurality of external connections.
18. The microcontroller according to claim 15 , wherein an output of the second output block is coupled to a fourth one of the plurality of external connections.
19. The microcontroller according to claim 15 , further comprising a mode selection input for selecting between the first mode and the second mode.
20. The microcontroller according to claim 19 , further comprising a fifth one of the plurality of external connections coupled to the mode selection input.
21. A method for configuring an amplifier as a programmable gain amplifier with a feedback network or an operational amplifier without any feedback network, said method comprising the steps of:
providing a differential input stage;
providing the feedback network;
providing a first output block having an input switchably coupled to an output of the differential input stage;
providing a second output block having an input switchably coupled to the output of the differential input stage; and
providing a plurality of switches coupled to the differential input stage, and the first and second output blocks;
coupling the differential input stage, the feedback network, and the first output block together as the programmable gain amplifier when the plurality of switches are arranged in a first mode;
coupling the differential input stage and the second output block together as an operational amplifier without any feedback network when the plurality of switches are arranged in a second mode, and
storing input offset calibration parameters for the differential input stage in an offset memory for the first and second modes.
22. The method according to claim 21 , further comprising the step of storing bias parameters for the differential input stage in a bias memory for the first and second modes.