Measuring output current in a buck SMPS
A sample and hold circuit takes a sample of the current flowing through an inductor of a buck switched-mode power supply (SMPS) at substantially the middle of the low side portion (50 percent point during low side switch ON) of the pulse width modulation (PWM) period. This sample of the current through the SMPS inductor during the low side ON 50% point may be considered as the “average” or “DC output” current of the SMPS, and taken every time at precisely the same low side ON 50%. A constant current source and sink are used to charge and discharge a timing capacitor whose voltage charge is monitored by a high speed voltage comparator to provide precise sample timing.
1. An apparatus for determining a power inductor current sample point in a buck switched-mode power supply (SMPS), comprising:
a constant current source having first and second nodes, wherein the first node thereof is coupled to a voltage source;
a constant current sink having first and second nodes, wherein the constant current sink is twice the current value of the constant current source;
a current source switch coupled between the second node of the constant current source and the first node of the constant current sink;
a current sink switch coupled between the second node of the constant current sink and a voltage source common;
a timing capacitor coupled between the first node of the constant current sink and the voltage source common;
a voltage comparator having a first input coupled to a predetermined reference voltage, a second input coupled to the timing capacitor and an output, wherein the output thereof is at a first logic level when the voltage on the timing capacitor is greater than the predetermined reference voltage, and at a second logic level when the voltage on the timing capacitor is equal to or less than the predetermined reference voltage; wherein
when a high side switch signal from the SMPS goes to a first logic level the current source switch turns on and couples the constant current source to the timing capacitor, whereby a voltage on the timing capacitor increases;
when the high side switch signal from the SMPS goes to a second logic level the current source switch turns off and decouples the constant current source from the timing capacitor, whereby the voltage on the timing capacitor stays the same; and
when a 50% pulse width modulation (PWM) period signal from the SMPS is received the current sink switch turns on and couples the constant current sink to the timing capacitor, whereby the voltage on the timing capacitor decreases twice as fast it increased when the high side switch signal is at the second logic level, and when the high side switch signal is at the first logic level the voltage on the timing capacitor decreases at the same rate as it increased.
2. The apparatus according to claim 1 , wherein when the output of the voltage comparator is at the second logic level a sample signal is generated.
3. The apparatus according to claim 2 , further comprising a voltage equalization switch coupled between the timing capacitor and the predetermined reference voltage, wherein when the sample signal is generated the voltage equalization switch turns on and forces the voltage on the timing capacitor to become substantially the same as the predetermined reference voltage.
4. The apparatus according to claim 3 , wherein a sample of the power inductor current is taken when the sample signal is generated.
5. A microcontroller comprising the apparatus of claim 1 .
6. A switched-mode power supply (SMPS) comprising:
high side and low side switches coupled in series between a supply voltage and common, and a power inductor coupled between a junction of the high side and low side switches and a load,
a current sampling timing and trigger logic circuit comprising:
a timing capacitor configured to be coupled with a first constant current source when the high side switch is on and to be discharged when a pulse width modulation (PWM) period of the SMPS reaches 50% and the high side switch is on; and
wherein the timing capacitor is further configured to be discharged with a second constant current when the PWM period reaches 50% and the high side switch is off, wherein the second constant current is twice the first constant current; and
wherein the current sampling timing and trigger logic circuit is further configured to sample a power inductor current when a voltage on the timing capacitor reaches a predetermined reference voltage.
7. The system according to claim 6 , wherein the timing capacitor is further configured not to be charged or discharged when the high side switch is off and the PWM period is less than 50%.
8. The system according to claim 6 , wherein said timing capacitor is further configured to be pre-charged to the reference voltage when the power inductor current is sampled.
9. The system according to claim 6 , further comprising an analog-to-digital converter (ADC) configured to convert the power inductor current sample into a digital representation thereof.
10. The system according to claim 6 , comprising
a current measurement resistor between the low side switch and the supply common; and
wherein the system is configured to sample a voltage developed across the current measurement resistor when the voltage on the timing capacitor reaches the predetermined reference voltage.
11. The system according to claim 6 , wherein the high side and low side switches are power transistors.
12. The system according to claim 11 , wherein the power transistors are metal oxide semiconductor field effect transistors (MOSFETs).
13. The system according to claim 12 , wherein the system is configured to sample a voltage developed across the low side MOSFET when the voltage on the timing capacitor reaches the predetermined reference voltage.
14. The system according to claim 12 , further comprising a pilot field effect transistor (FET) associated with the low side MOSFET, wherein the pilot FET has a small portion of the power inductor current flowing therethrough; and
wherein the system is configured to sample a voltage developed across the pilot FET and the low side MOSFET when the voltage on the timing capacitor reaches the predetermined reference voltage.
15. The system according to claim 6 , further comprising a current measurement resistor in series with the power inductor; and
wherein the system is configured to sample a voltage developed across the current measurement resistor when the voltage on the timing capacitor reaches the predetermined reference voltage.
16. The system according to claim 6 , wherein the system is configured to sample a voltage across the power inductor when the voltage on the timing capacitor reaches the predetermined reference voltage.
17. The system according to claim 6 , wherein the predetermined threshold voltage is approximately zero (0) volts.
18. The system according to claim 6 , wherein the system is configured to generate a sample signal when the voltage on the timing capacitor reaches the predetermined reference voltage.
19. The system according to claim 6 , further comprising an analog-to-digital converter (ADC) configured to convert the power inductor current sample into a digital representation thereof every n th time the voltage on the timing capacitor reaches the predetermined reference voltage.