Timed multiplex sensing
Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
1. An apparatus, comprising:
a plurality of memory cells including a first memory cell connected to a first bit line and a second memory cell connected to a second bit line;
one or more managing circuits configured to determine a first sensing time associated with the first memory cell and determine a second sensing time associated with the second memory cell; and
a read circuit in communication with the first bit line and the second bit line, the read circuit configured to integrate a first current associated with the first bit line during the first sensing time and integrate a second current associated with the second bit line during the second sensing time, the read circuit configured to detect a first state of the first memory cell based on the integration of the first current and a reference voltage using a detection block during a first time period, the read circuit configured to detect a second state of the second memory cell based on the integration of the second current and the reference voltage using the detection block during a second time period subsequent to the first time period.
2. The apparatus of claim 1 , wherein:
the second sensing time is greater than the first sensing time.
3. The apparatus of claim 1 , wherein:
the second sensing time overlaps with the first time period during which the first state is determined.
4. The apparatus of claim 1 , wherein:
the detection block comprises a comparator.
5. The apparatus of claim 4 , wherein:
the comparator is time multiplexed such that the first state of the first memory cell is determined using the comparator during the first time period and the second state of the second memory cell is determined using the comparator during the second time period.
6. The apparatus of claim 1 , wherein:
the one or more managing circuits configured to determine the first sensing time based on a number of read errors associated with the first bit line.
7. The apparatus of claim 1 , wherein:
the first bit line comprises a vertical bit line.
8. The apparatus of claim 1 , wherein:
the first memory cell is associated with a vertical NAND string.
9. The apparatus of claim 1 , wherein:
the first memory cell comprises a two-terminal memory cell.
10. The apparatus of claim 1 , wherein:
the read circuit is arranged on a memory die that includes non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.
11. A system, comprising:
a controller configured to determine a first sensing time associated with a first memory cell connected to a first bit line and determine a second sensing time associated with a second memory cell connected to a second bit line; and
a read circuit configured to integrate a first current associated with the first bit line during the first sensing time and integrate a second current associated with the second bit line during the second sensing time, the read circuit configured to determine a first state of the first memory cell based on the integration of the first current and a reference voltage using a comparator during a first time period, the read circuit configured to determine a second state of the second memory cell based on the integration of the second current and the reference voltage using the comparator during a second time period subsequent to the first time period, the second sensing time overlaps with the first time period during which the first state is determined.
12. The system of claim 11 , wherein:
the second sensing time is greater than the first sensing time.
13. The system of claim 11 , wherein:
the comparator is time multiplexed such that the first state of the first memory cell is determined using the comparator during the first time period and the second state of the second memory cell is determined using the comparator during the second time period.
14. The system of claim 11 , wherein:
the controller configured to determine the first sensing time based on a number of read errors associated with the first bit line.
15. The system of claim 11 , wherein:
the first bit line comprises a vertical bit line.
16. The system of claim 11 , wherein:
the first memory cell is associated with a vertical NAND string.
17. The system of claim 11 , wherein:
the first memory cell comprises a two-terminal memory cell.
18. A non-volatile storage system, comprising:
a memory array including a first memory cell connected to a first bit line and a second memory cell connected to a second bit line;
one or more control circuits configured to determine a first sensing time associated with the first memory cell and determine a second sensing time associated with the second memory cell; and
a read circuit configured to integrate a first current associated with the first bit line during the first sensing time and integrate a second current associated with the second bit line during the second sensing time, the read circuit configured to detect a first state of the first memory cell based on the integration of the first current during a first time period, the read circuit configured to detect a second state of the second memory cell based on the integration of the second current during a second time period subsequent to the first time period, the second sensing time overlaps with the first time period during which the first state is detected.
19. The non-volatile storage system of claim 18 , wherein:
the second sensing time is greater than the first sensing time.
20. The non-volatile storage system of claim 18 , wherein:
the read circuit is arranged on a memory die that includes non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate, the first bit line comprises a vertical bit line that is orthogonal to a substrate of the memory die.