Automatic gain control for received signal strength indication
View Patent ↗In some implementations, an automatic gain control (AGC) circuit comprises: a pre-divider circuit operable to pre-divide an input signal according to a pre-divider circuit setting and output a pre-divided signal; a pre-amplifier operable to pre-amplify the pre-divided signal and output a pre-amplified signal; a post-divider circuit operable to post-divide the pre-amplified signal according to a post-divider circuit setting; an analog-to-digital converter (ADC) operable to generate a digital data stream from the post-divided signal; logic operable to sample the digital data stream; determine a pre-divider circuit setting and a post-divider circuit setting based on the sampled data stream; set the pre-divider circuit and the post-divider circuit based on the determined settings; and generate a received signal strength value based on the pre-divider circuit setting and the post-divider circuit setting.
1. An automatic gain control (AGC) circuit, comprising:
a pre-divider circuit operable to pre-divide an input analog signal according to a pre-divider circuit setting and output a pre-divided analog signal;
a pre-amplifier operable to pre-amplify the pre-divided analog signal and output a pre-amplified analog signal;
a post-divider circuit operable to post-divide the pre-amplified analog signal according to a post-divider circuit setting and output a post-divided analog signal;
an analog-to-digital converter (ADC) operable to convert the post-divided analog signal into a digital data stream; and
logic operable to:
sample the digital data stream;
determine a pre-divider circuit setting and a post-divider circuit setting based on the sampled data stream;
set the pre-divider circuit and the post-divider circuit based on the determined settings; and
generate a received signal strength value based on the pre-divider circuit setting and the post-divider circuit setting.
2. The AGC circuit of claim 1 , wherein the digital data stream represents an instantaneous amplitude of the input analog signal at the ADC input during a current period of the input analog signal.
3. The AGC circuit of claim 1 , wherein the post-divider circuit can be configured to have different resolutions.
4. The AGC circuit of claim 1 , further comprising:
a post-amplifier between the post-divider circuit and the ADC input, the post-amplifier circuit operable to post-amplify the post-divided analog signal.
5. The AGC circuit of claim 1 , further comprising:
a bandpass filter inserted between antenna input terminals and the input of the ADC.
6. The AGC circuit of claim 1 , wherein at least one of the pre-divider circuit is operable to bypass the input analog signal based on a strength of the input analog signal and the post-divider circuit is operable to bypass the pre-amplified input analog signal based on a strength of the pre-amplified analog signal.
7. The AGC circuit of claim 1 , wherein at least one of the pre-divider circuit and the post-divider circuit are configured as logarithmic dividers.
8. The AGC circuit of claim 1 , wherein the ADC is a flash ADC.
9. The AGC circuit of claim 8 , wherein the flash ADC is an offset compensated flash ADC.
10. The AGC circuit of claim 1 , wherein the logic is further operable to:
sample the digital data stream over a period of the input analog signal;
detect a peak value from the sample; and
determine the pre-divider and post-divider circuit settings based on the detected peak value.
11. The AGC circuit of claim 1 , wherein the logic is further operable to:
sample the digital data stream ninety degrees after a zero crossing of the input analog signal; and
determine the pre-divider and post-divider circuit settings based on the detected peak value.
12. The AGC circuit of claim 1 , wherein the pre-divider circuit is configured to have input impedance that is substantially constant for all pre-divider circuit settings.
13. The AGC circuit of claim 1 , wherein the logic is further configured to send feedback values to the pre-divider circuit and to the post-divider circuit every n period(s) of the input analog signal for use in setting the pre-divider circuit and the post-divider circuit, where n is a positive integer greater or equal to one.
14. The AGC circuit of claim 13 , wherein the feedback values are averaged to reduce an amount of data.
15. The AGC circuit of claim 14 , wherein the feedback values are averaged based on at least one of a number of feedback values that occurred during a time period.
16. The AGC circuit of claim 1 , wherein the received signal strength values are determined by ADC samples in combination with values of the pre-divider circuit and post-divider circuit.
17. The AGC circuit of claim 1 , wherein the AGC circuit is further configured to:
store calibration data for individual pre-divider circuit attenuations to increase an accuracy over a complete range of received signal strength values.
18. The AGC circuit of claim 1 , where the logic is further configured to:
enforce the pre-divider to a range setting;
measure one or more averaged post-divider values that result from a constant and continuous wave signal at the AGC circuit input after the AGC circuit has settled in a first calibration measurement;
enforce the pre-divider to a next range setting and measure one or more averaged post-divider values that result from the constant and continuous wave signal at the AGC circuit input after the AGC circuit has settled and by maintaining an amplitude of the signal at a level related to a preceding measurement for a second calibration measurement;
store a difference of post-divider values derived from the first and second calibration measurements as a calibration value;
repeat the calibration measurement and store steps for other ranges; and
calculate each received signal strength value from a current measured post-divider value and from a summation of stored pre-divider calibration values of ranges which are less than or equal to a current range setting.
19. A method of automatic gain control (AGC) performed by an AGC circuit, comprising:
pre-dividing, by a pre-divider circuit, an input analog signal according to a pre-divider circuit setting and outputting a pre-divided analog signal;
pre-amplifying, by a pre-amplifier, the pre-divided analog signal and outputting a pre-amplified analog signal;
post-dividing, by a post-divider circuit, the pre-amplified analog signal according to a post-divider circuit setting;
generating, by an analog-to-digital converter (ADC), a digital data stream from the post-divided analog signal;
sampling the digital data stream;
determining a pre-divider circuit setting and a post-divider circuit setting based on the sampled digital data stream;
setting the pre-divider circuit and the post-divider circuit based on the determined settings; and
generating a received signal strength value based on the pre-divider circuit setting and the post-divider circuit setting.
20. The method of claim 19 , wherein the digital data stream represents instantaneous amplitude values of the input analog signal at the ADC for every signal period.
21. The method of claim 19 , further comprising:
bypassing, by the pre-divider circuit, the input analog signal based on a strength of the input analog signal; or
bypassing, by the post-divider circuit, the pre-amplified input analog signal based on a strength of the pre-amplified analog signal.
22. The method of claim 19 , further comprising:
sampling the digital data stream over a period of the input analog signal;
detecting a peak value from the sample; and
determining the pre-divider and post-divider circuit settings based on the detected peak value.
23. The method of claim 19 , further comprising:
sampling the digital data stream ninety degrees after a zero crossing of the input analog signal; and
determining the pre-divider and post-divider circuit settings based on the detected peak value.
24. The method claim 19 , further comprising:
sending feedback values to the pre-divider circuit and to the post-divider circuit every n period(s) of the input analog signal for use in setting the pre-divider circuit and the post-divider circuit, where n is a positive integer greater or equal to one.
25. The method of claim 19 , further comprising:
storing calibration data for individual pre-divider circuit attenuations to increase an accuracy over a complete range of received signal strength values.
26. The method of claim 19 , further comprising:
enforcing the pre-divider to a range setting;
measuring one or more averaged post-divider values that result from the input analog signal after the AGC circuit has settled in a first calibration measurement;
enforcing the pre-divider to a next range setting and measure one or more averaged post-divider values that result from the input analog signal after the AGC circuit has settled and by maintaining an amplitude of the input analog signal at a level related to a preceding measurement for a second calibration measurement;
storing a difference of post-divider values derived from the first and second calibration measurements as a calibration value;
repeating the calibration measurement and store steps for other ranges; and
calculating each received signal strength value from a current measured post-divider value and from a summation of stored pre-divider calibration values of ranges which are less than or equal to a current range setting.