Semiconductor device with voids within silicon-on-insulator (SOI) structure and method of forming the semiconductor device
A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void.
1. A method of forming a semiconductor device with a void within a silicon-on-insulator (SOI) structure, the method comprising:
forming a silicon-on-insulator (SOI) substrate comprising
a semiconductor substrate,
an insulating layer on the semiconductor substrate, and
a semiconductor layer;
forming an opening of the semiconductor layer;
performing an isotropic etch process to form a void in the insulating layer; and
sealing the opening of the semiconductor layer.
2. The method of claim 1 , wherein the void extends laterally from the opening of the semiconductor layer.
3. The method of claim 1 , wherein the void is sealed by a thermal oxidation method or a chemical vapor deposition (CVD) method.
4. The method of claim 1 , wherein the sealing of the void comprises filing the gap region with another insulating layer.
5. The method of claim 1 , further comprising forming a device isolation layer on the semiconductor layer before the opening of the semiconductor layer is formed.
6. The method of claim 5 , wherein the forming of the device isolation layer comprises:
forming at least one trench in the semiconductor layer through a mask process;
forming an anti-etching layer at sides of the at least one trench; and
filing the at least one trench with an insulating material.
7. The method of claim 1 , further comprising forming a void-protection layer on a surface of the void.
8. The method of claim 1 , further comprising forming a device isolation layer on the semiconductor layer after the sealing the opening of the semiconductor layer.
9. The method of claim 1 , wherein the opening is formed by an anisotropic etching method.
10. The method of claim 6 , wherein the anti-etching layer is a silicon nitride layer.
11. The method of claim 1 , wherein the void in the insulating layer has a width larger than that of the opening of the semiconductor layer.
12. The method of claim 1 , wherein the isotropic etch process comprises a wet etching process.
13. The method of claim 1 , wherein the void in the insulating layer is formed by a wet etching process.
14. The method of claim 1 , wherein the opening of the semiconductor layer does not extend to the insulating layer.
15. The method of claim 1 , wherein the opening is formed by selectively etching the semiconductor layer.