Managing wait states for memory access
A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.
1. A method comprising:
receiving, at a device controller, a first latch signal from a peripheral device that indicates start of an access operation at the peripheral device;
setting, by the device controller, an internal delay signal to a first state based on the first latch signal;
in response to setting the internal delay signal to the first state, setting a system bus data ready signal to the first state to indicate start of a wait state associated with the access operation at the peripheral device, wherein the internal delay signal is distinct from the system bus data ready signal;
receiving a second latch signal from the peripheral device that indicates that the access operation is completed; and
setting the system bus data ready signal to a second state to indicate completion of the wait state based on the second latch signal.
2. The method of claim 1 , wherein setting the internal delay signal to the first state based on the first latch signal comprises:
setting the internal delay signal to the first state based on adjusting the first latch signal with a system bus clock signal.
3. The method of claim 2 , wherein setting the internal delay signal to the second state based on the second latch signal comprises:
setting the internal delay signal to the second state based on adjusting the second latch signal with a system bus clock signal.
4. The method of claim 2 , wherein the system bus clock signal varies over time depending on an application executed by a central processing unit (CPU) associated with the peripheral device, and wherein the wait state is independent of a frequency of the system bus clock signal.
5. The method of claim 1 , wherein the first latch signal corresponds to a first edge of a latch signal that indicates a start time for processing the access operation at the peripheral device, and wherein the second latch signal corresponds to a second edge of the latch signal that indicates an end to the processing of the access operation at the peripheral device.
6. The method of claim 5 , wherein the first or the second edge of the latch signal corresponds to a current access time for the peripheral device, and wherein receiving the first edge or the second edge of the latch signal includes:
evaluating a data ready edge of the latch signal; and
based on the evaluation, automatically increasing or decreasing the wait state depending on the current access time for the peripheral device, wherein increasing or decreasing the wait state respectively includes delaying or accelerating a triggering of the system bus data ready signal.
7. The method of claim 1 , wherein setting the system bus data ready signal to the first state or the second state comprises:
setting the system bus data ready signal to the first state or the second state after a finite amount of time subsequent to receipt of the first latch signal or the second latch signal respectively, comprising:
setting the system bus data ready signal to the first state or the second state after elapse of a complete cycle of a system bus clock signal subsequent to receiving the first latch signal or the second latch signal.
8. The method of claim 1 , wherein setting the system bus data ready signal to the first state in response to setting the internal delay signal to the first state comprises:
upon setting the internal delay signal to the first state, waiting for a next cycle of a system bus clock signal;
receiving a leading edge of the next cycle of the system bus clock signal following setting the internal delay signal to the first state; and
in response to receiving the leading edge of the next cycle of the system bus clock signal when the internal delay signal is in the first state, setting the system bus data ready signal to the first state.
9. The method of claim 8 , wherein setting the system bus data ready signal to the second state based on the second latch signal comprises:
in response to receiving the second latch signal from the peripheral device, transitioning the internal delay signal from the first state to the second state;
upon transitioning the internal delay signal to the second state, waiting for a next cycle of a system bus clock signal;
receiving a leading edge of the next cycle of the system bus clock signal following transitioning the internal delay signal to the second state; and
in response to receiving the leading edge of the next cycle of the system bus clock signal when the internal delay signal is in the second state, setting the system bus data ready signal to the second state.
10. The method of claim 1 , wherein the wait state is based on an amount of time used to perform the access operation at the peripheral device, the amount of time depending on one or more of temperature, voltage, semiconductor material, process deviation or frequency of access.
11. The method of claim 1 , wherein the peripheral device includes a memory device and wherein the access operation at the memory device corresponds to a data access operation at the memory device.
12. The method of claim 11 , wherein the first latch signal or the second latch signal corresponds to an amount of time used to access physical memory locations in the memory device in response to a data access request associated with the memory device.
13. A system comprising:
a peripheral device; and
a device controller coupled to the peripheral device, the device controller configured to perform operations comprising:
receiving a first latch signal from the peripheral device that indicates start of an access operation at the peripheral device;
setting an internal delay signal to a first state based on the first latch signal;
in response to setting the internal delay signal to the first state, setting a system bus data ready signal to the first state to indicate start of a wait state associated with the access operation at the peripheral device, wherein the internal delay signal is distinct from the system bus data ready signal;
receiving a second latch signal from the peripheral device that indicates that the access operation is completed; and
setting the system bus data ready signal to a second state to indicate completion of the wait state based on the second latch signal.
14. The system of claim 13 , wherein setting the internal delay signal to the first state based on the first latch signal comprises:
setting the internal delay signal to the first state based on adjusting the first latch signal with a system bus clock signal.
15. The system of claim 14 , wherein setting the internal delay signal to the second state based on the second latch signal comprises:
setting the internal delay signal to the second state based on adjusting the second latch signal with a system bus clock signal.
16. The system of claim 14 , wherein the system bus clock signal varies over time depending on an application executed by a central processing unit (CPU) associated with the peripheral device, and wherein the wait state is independent of a frequency of the system bus clock signal.
17. The system of claim 13 , wherein the first latch signal corresponds to a first edge of a latch signal that indicates a start time for processing the access operation at the peripheral device, and wherein the second latch signal corresponds to a second edge of the latch signal that indicates an end to the processing of the access operation at the peripheral device.
18. The system of claim 17 , wherein the first or the second edge of the latch signal corresponds to a current access time for the peripheral device, and wherein receiving the first edge or the second edge of the latch signal includes:
evaluating a data ready edge of the latch signal; and
based on the evaluation, automatically increasing or decreasing the wait state depending on the current access time for the peripheral device, wherein increasing or decreasing the wait state respectively includes delaying or accelerating a triggering of the system bus data ready signal.
19. The system of claim 13 , wherein setting the system bus data ready signal to the first state or the second state comprises:
setting the system bus data ready signal to the first state or the second state after a finite amount of time subsequent to receipt of the first latch signal or the second latch signal respectively, comprising:
setting the system bus data ready signal to the first state or the second state after elapse of a complete cycle of a system bus clock signal subsequent to receiving the first latch signal or the second latch signal.
20. The system of claim 13 , wherein setting the system bus data ready signal to the first state in response to setting the internal delay signal to the first state comprises:
upon setting the internal delay signal to the first state, waiting for a next cycle of a system bus clock signal;
receiving a leading edge of the next cycle of the system bus clock signal following setting the internal delay signal to the first state; and
in response to receiving the leading edge of the next cycle of the system bus clock signal when the internal delay signal is in the first state, setting the system bus data ready signal to the first state.
21. The system of claim 20 , wherein setting the system bus data ready signal to the second state based on the second latch signal comprises:
in response to receiving the second latch signal from the peripheral device, transitioning the internal delay signal from the first state to the second state;
upon transitioning the internal delay signal to the second state, waiting for a next cycle of a system bus clock signal;
receiving a leading edge of the next cycle of the system bus clock signal following transitioning the internal delay signal to the second state; and
in response to receiving the leading edge of the next cycle of the system bus clock signal when the internal delay signal is in the second state, setting the system bus data ready signal to the second state.
22. The system of claim 13 , wherein the wait state is based on an amount of time used to perform the access operation at the peripheral device, the amount of time depending on one or more of temperature, voltage, semiconductor material, process deviation or frequency of access.
23. The system of claim 13 , wherein the peripheral device includes a memory device and wherein the access operation at the memory device corresponds to a data access operation at the memory device.
24. The system of claim 23 , wherein the first latch signal or the second latch signal corresponds to an amount of time used to access physical memory locations in the memory device in response to a data access request associated with the memory device.