IP Library Granted Patent US 10,204,057
Granted Patent B2
US 10,204,057 · App. 15/294,413 · Granted Feb 12, 2019

Memory emulation mechanism

Inventors: Frode Milch Pedersen (Trondheim, NO); Sylvain Garnier (Nantes, FR); Ian Fullerton (Los Gatos, CA); Xavier Leprevost (Saint Mars du Desert, FR)
Assignee: Atmel Corporation
G06F12/1009G06F3/0611G06F3/0659G06F3/0679G06F12/0246G06F2212/2022G06F2212/7201
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Quick Facts
Patent No.
US 10,204,057
App. No.
15/294,413
Filed
Oct 14, 2016
Granted
Feb 12, 2019
Kind
B2
Art Unit
2131
USPC
711/103
Abstract

In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

Claims (66)

1. A method comprising:

obtaining, by a memory controller, a virtual bus address;

translating, by the memory controller, the virtual bus address to a physical address of a first portion of non-volatile memory (NVM) storing first data;

determining, by the memory controller, that the first portion of NVM is currently allocated;

reading, by the memory controller, the first data from the first portion of NVM;

determining, by the memory controller, whether writing second data to the first portion of the NVM would change one or more bits in the first data;

responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM;

responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data;

obtaining, by the memory controller, a virtual pointer to the physical address from an index stored in the NVM, wherein the index includes a next pointer pointing to a next unallocated portion of NVM;

translating, by the memory controller, the virtual bus address to the physical address using the virtual pointer;

determining that a new portion of the NVM needs to be allocated; and

copying the next pointer to the virtual pointer in the index.

2. The method of claim 1 , wherein most significant bits of the virtual bus address are used to identify the first portion of NVM and least significant bits of the virtual bus address are used to identify a position in the first portion of NVM to be accessed.

3. The method of claim 1 , further comprising:

determining, by using a virtual pointer, that the first portion of NVM has not been allocated;

allocating the first portion of NVM; and

writing the first data into the first portion of NVM.

4. The method of claim 1 , further comprising:

determining a write mode; and

writing the second data over the first data according to the write mode.

5. The method of claim 4 , further comprising:

determining that the write mode is a buffer mode;

writing the second data to a buffer; and

writing the second data from the buffer into the second portion of NVM when another portion of NVM is addressed.

6. The method of claim 1 , further comprising:

determining that there are no unallocated portions of NVM in a first sector of NVM;

copying allocated portions of NVM to a second sector of NVM; and

erasing the first sector of NVM.

7. The method of claim 6 , further comprising:

determining that a previously allocated portion of NVM is deallocated; and

excluding the deallocated portion of NVM from the copying to the second sector of NVM.

8. The method of claim 6 , wherein the first and second sectors are located in portions of the NVM with read-while-write properties.

9. A system comprising:

non-volatile memory (NVM); and

a memory controller coupled to the NVM, the memory controller:

obtaining a virtual bus address;

translating the virtual bus address to a physical address of a first portion of non-volatile memory (NVM) storing first data;

determining that the first portion of NVM is currently allocated;

reading the first data from the first portion of NVM;

determining whether writing second data to the first portion of the NVM would change one or more bits in the first data;

responding to the determining that a write operation only changes data bits in the first data from 1 to 0 by writing the second data over the first data stored in the first portion of NVM;

responding to the determining that one or more bits in the first data would be flipped from 0 to 1 by reallocating the first portion of NVM to a second portion of NVM, and copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data;

obtaining, by the memory controller, a virtual pointer to the physical address from an index stored in the NVM, wherein the index includes a next pointer pointing to a next unallocated portion of NVM;

translating, by the memory controller, the virtual bus address to the physical address using the virtual pointer;

determining that a new portion of NVM needs to be allocated; and

copying the next pointer to the virtual pointer in the index.

10. The system of claim 9 , wherein most significant bits of the virtual bus address are used to identify the first portion of NVM and least significant bits of the virtual bus address are used to identify a position in the first portion of NVM to be accessed.

11. The system of claim 9 , further comprising:

determining, by the virtual pointer, that the first portion of NVM has not been allocated;

allocating the first portion of NVM; and

writing the first data into the first portion of NVM.

12. The system of claim 9 , further comprising:

determining a write mode; and

writing the second data over the first data according to the write mode.

13. The system of claim 12 , further comprising:

determining that the write mode is a buffer mode;

writing the second data to a buffer; and

writing the second data from the buffer into the second portion of NVM when another portion of NVM is addressed.

14. The system of claim 9 , further comprising:

determining that there are no unallocated portions of NVM in a first sector of NVM;

copying allocated portions of NVM to a second sector of NVM; and

erasing the first sector of NVM.

15. The system of claim 14 , further comprising:

determining that a previously allocated portion of NVM is deallocated; and

excluding the deallocated portion of NVM from the copying to the second sector of NVM.

16. The system of claim 14 , wherein the first and second sectors are located in portions of the NVM with read-while-write properties.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2017
From: ATMEL NANTES S.A.S.
To: ATMEL CORPORATION
Reel/Frame 040844/0594 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2016
From: PEDERSEN, FRODE MILCH; FULLERTON, IAN
To: ATMEL CORPORATION
Reel/Frame 040791/0114 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2016
From: GARNIER, SYLVAIN; LEPREVOST, XAVIER
To: ATMEL NANTES S.A.S.
Reel/Frame 040791/0162 →
Continuity (2)
Provisional Application 62372726 · Aug 9, 2016
Related Publication 20180046582A1 · Feb 15, 2018