Apparatuses and methods for converting fluctuations in periodicity of an input signal into fluctuations in amplitude of an output signal
An exemplary apparatus for converting fluctuations in periodicity of an input signal into proportional fluctuations in the amplitude of an output signal includes: an input line for accepting an input signal; a delay element with an input coupled to the input line and an output; a detector having a first input coupled to the input line, a second input coupled to the output of the delay element, and an output; an integrator having an input coupled to the output of the detector and an output; and an output line coupled to the output of the integrator. The delay element introduces a time delay which is greater than zero and less than twice the nominal oscillation period of the input signal. The detector performs a differencing operation. The integrator has a time constant of integration that is smaller than twice the delay applied by the delay element.
1. An apparatus for converting fluctuations in periodicity of an input signal into proportional fluctuations in the amplitude of an output signal, comprising:
an input line for accepting an input signal that transitions between high and low states with a nominal oscillation period which fluctuates in at least one of frequency and/or phase;
a delay element with an input coupled to the input line and an output;
a detector having a first input coupled to the input line, a second input coupled to the output of the delay element, and an output;
an integrator having an input coupled to the output of the detector and an output; and
an output line coupled to the output of the integrator,
wherein said delay element introduces a time delay that rounds to at least one oscillation period such that signal transitions taking place during a time interval associated with a current oscillation period are caused to instead take place during a time interval associated with a subsequent oscillation period,
wherein said detector performs a differencing operation with an associated differentiator response, and produces an output signal which is proportional, in at least one of an amplitude or a pulse width, to dynamic timing differences between transitions in a signal coupled to its first input and transitions in a signal coupled its second input, and
wherein a time constant of said integrator and a delay introduced by said delay element reflect a same number of oscillation periods, causing said integrator to produce a response that counteracts the differentiator response of said detector and to produce an output with an amplitude that tracks fluctuations in at least one of a frequency or a phase of said input signal.
2. An apparatus according to claim 1 , wherein said detector senses a difference in timing between logic transitions of a signal provided to a first input and a signal provided to a second input, and produces a pulse-width modulated output that is proportional to said difference in timing.
3. An apparatus according to claim 2 , wherein said detector includes at least one of a conventional phase/frequency detector or a logic gate that performs an exclusive-OR function.
4. An apparatus according to claim 1 , wherein said detector senses a difference in phase between a signal provided to a first input and a signal provided to a second input, and produces an amplitude modulated output that is proportional to said difference in phase.
5. An apparatus according to claim 4 , wherein said detector includes at least one of an analog multiplier or a diode-bridge mixer.
6. An apparatus according to claim 1 , further comprising and least one frequency counter which is coupled to an input of said detector, and which reduces the frequency of a signal provided to the input of said detector.
7. An apparatus according to claim 1 , further comprising an offset correction circuit that compensates for static offsets at the output of said apparatus, which are produced by static differences in the timing or phase between signals provided to the first and second inputs of said detector.
8. An apparatus according to claim 7 , wherein said offset correction circuit utilizes a local feedback loop to minimize the mean level of at least one of an input or an output of said integrator.
9. An apparatus according to claim 7 , wherein said offset correction circuit makes an adjustment to at least one of a mean input level or a mean output level of said integrator, such that the level of residual quantization noise is minimized at the output of a sampling/quantization circuit.
10. An apparatus according to claim 1 , further comprising an analog-to-digital converter that couples an output of said detector, which is continuous in time and in value, to an input of said integrator, which is discrete in time and in value.