IP Library Granted Patent US 10,073,624
Granted Patent B2
US 10,073,624 · App. 15/402,522 · Granted Sep 11, 2018

Memory system

Inventor: Shinken Okamoto (Shizuoka, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F3/0605G06F3/064G06F3/0619G06F3/0653G06F3/0659G06F3/0679G06F11/1072G06F11/1084G06F11/3034G06F11/3058G06F11/327G06F12/0246G11C29/50004G06F2212/1032G06F2212/152G06F2212/214G06F2212/7201G06F2212/7207G06F2212/7211G11C16/14G11C16/16G11C16/349G11C16/3445G11C29/52G11C2029/5004
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Quick Facts
Patent No.
US 10,073,624
App. No.
15/402,522
Granted
Sep 11, 2018
Kind
B2
Abstract

According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.

Claims (16)

1. A system comprising:

a semiconductor nonvolatile memory configured to store data;

a management unit configured to manage the semiconductor nonvolatile memory; and

a control unit configured to input a first voltage to a specific block of the semiconductor nonvolatile memory a plurality of times in response to a single command from a host, the single command being a command for a single erase operation or a single write operation to be performed on the semiconductor nonvolatile memory, wherein

the semiconductor nonvolatile memory includes blocks for at least one of management, replacement, and buffering, the semiconductor nonvolatile memory being configured to store data received from the host via a host interface,

the control unit is configured to control the semiconductor nonvolatile memory on the basis of information indicating correlation between a logical address specified by the host and a physical address of the semiconductor nonvolatile memory,

the management unit is configured to determine degradation of the specific block on the basis of a loop count of the first voltage that was input to the specific block in response to the single command, the loop count being a number of pulses of the first voltage applied to the semiconductor nonvolatile memory in the single erase operation or the single write operation, and

the management unit is configured to cause a display device to display a warning when a number of blocks related to the degradation reaches a first threshold.

2. A system comprising:

a semiconductor nonvolatile memory configured to store data;

a management unit configured to manage the semiconductor nonvolatile memory; and

a control unit configured to input a first voltage to a specific block of the semiconductor nonvolatile memory a plurality of times in response to a single command from a host, the single command being a command for a single erase operation or a single write operation to be performed on the semiconductor nonvolatile memory, wherein

the semiconductor nonvolatile memory includes blocks for at least one of management, replacement, and buffering, the semiconductor nonvolatile memory being configured to store data received from the host via a host interface,

the control unit is configured to control the semiconductor nonvolatile memory on the basis of information indicating correlation between a logical address specified by the host and a physical address of the semiconductor nonvolatile memory,

the management unit is configured to determine degradation of the specific block on the basis of a loop count of the first voltage that was input to the specific block in response to the single command, the loop count being a number of pulses of the first voltage applied to the semiconductor nonvolatile memory in the single erase operation or the single write operation, and

the management unit is configured to store information to be output to an external device when a number of blocks related to the degradation reaches a first threshold.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043088/0620 →
Priority Claims (1)
JP 2010-027944 · Feb 10, 2010 · national
Continuity (6)
Continuation 15135953 · Apr 22, 2016
Continuation 14677361 · Apr 2, 2015
Continuation 14300784 · Jun 10, 2014
Continuation 14070020 · Nov 1, 2013
Continuation 12886260 · Sep 20, 2010
Related Publication 20170123673A1 · May 4, 2017