IP Library Granted Patent US 10,109,504
Granted Patent B2
US 10,109,504 · App. 15/419,840 · Granted Oct 23, 2018

Wafer manufacturing cleaning apparatus, process and method of use

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Quick Facts
Patent No.
US 10,109,504
App. No.
15/419,840
Granted
Oct 23, 2018
Kind
B2
Abstract

A cleaning wafer or substrate for use in cleaning, or in combination with, components of, for example, integrated chip manufacturing apparatus. The cleaning substrate can include a substrate having varying predetermined surface features, such as one or more predetermined adhesive, non-tacky, electrostatic, projection, depression, or other physical sections. The predetermined features can provide for more effective cleaning of the components with which they are used, such as an integrated chip manufacturing apparatus in the place of the integrated chip wafer. The cleaning substrate can be urged into cleaning or other position by vacuum, mechanical, electrostatic, or other forces. The cleaning substrate can adapted to accomplish a variety of functions, including abrading or polishing. The cleaning substrate may be made by a novel method of making, and it may then be used in a novel method of use I combination with chip manufacturing apparatus.

Claims (9)

1. A method of cleaning a semiconductor manufacturing apparatus with a cleaning wafer comprising a resilient cleaning pad having a cleaning side with a tacky area and a compressible projection protruding from the cleaning side, the method comprising:

mounting the cleaning wafer on the semiconductor manufacturing apparatus;

applying a force to urge the cleaning side against a surface of the semiconductor manufacturing apparatus and thereby compress the compressible projection; and

releasing the force whereby the compressible projection decompresses, urging the cleaning side away from the surface.

2. The method of claim 1 wherein:

the tacky area has two sub-areas of differing thicknesses and mounting the cleaning wafer comprises orienting the cleaning wafer to align at least one of the sub-areas with a predetermined non-planar surface of the semiconductor manufacturing apparatus.

3. The method of claim 1 wherein:

the tacky area has two sub-areas of differing levels of tack and mounting the cleaning wafer comprises orienting the cleaning wafer to align the two sub-areas with a predetermined surface of the semiconductor manufacturing apparatus.

4. The method of claim 1 wherein the tacky area of the cleaning pad is planar.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2023
From: INTERNATIONAL TEST SOLUTIONS, LLC
To: ENTEGRIS, INC.
Reel/Frame 065764/0493 →
SECURITY INTEREST Recorded Jul 8, 2022
From: ENTEGRIS, INC.; ENTEGRIS GP, INC.; POCO GRAPHITE, INC.; CMC MATERIALS, INC.; INTERNATIONAL TEST SOLUTIONS, LLC; QED TECHNOLOGIES INTERNATIONAL, INC.
To: TRUIST BANK, AS NOTES COLLATERAL AGENT
Reel/Frame 060613/0072 →
SECURITY INTEREST Recorded Jul 8, 2022
From: CMC MATERIALS, INC.; INTERNATIONAL TEST SOLUTIONS, LLC; QED TECHNOLOGIES INTERNATIONAL, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 060615/0001 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2022
From: JPMORGAN CHASE BANK, N.A.
To: CABOT MICROELECTRONICS CORPORATION; QED TECHNOLOGIES INTERNATIONAL, INC.; FLOWCHEM LLC; KMG ELECTRONIC CHEMICALS, INC.; KMG-BERNUTH, INC.; MPOWER SPECIALTY CHEMICALS LLC; SEALWELD (USA), INC.; INTERNATIONAL TEST SOLUTIONS, LLC; CMC MATERIALS, INC.
Reel/Frame 060592/0260 →
CHANGE OF NAME Recorded May 3, 2021
From: INTERNATIONAL TEST SOLUTIONS, INC.
To: INTERNATIONAL TEST SOLUTIONS, LLC
Reel/Frame 056121/0757 →
SECURITY AGREEMENT Recorded Apr 30, 2021
From: INTERNATIONAL TEST SOLUTIONS, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 056104/0979 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2021
From: HUMPHREY, ALAN E.; DUVALL, JAMES H.; BROZ, JERRY J.
To: INTERNATIONAL TEST SOLUTIONS, INC.
Reel/Frame 055500/0329 →