Time-based delay line analog-to-digital converter with variable resolution
Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.
1. A differential digital delay line analog-to-digital converter (ADC), comprising:
differential digital delay lines comprising a plurality of series coupled delay cells, wherein a delay time of a first delay line is controlled by a first voltage at an input of the ADC and a delay time of a second delay line is controlled by a second voltage at the input of the ADC;
a first pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells;
a plurality of latches each coupled with the series coupled delay cells;
a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC; and
a plurality of logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.
2. The ADC of claim 1 , wherein the first pair of bypass multiplexers is placed at a 50% point of the series coupled delay cells.
3. The ADC of claim 1 , further comprising a second pair of bypass multiplexers placed at a 50% point between the first pair of bypass multiplexers and a delay line end, wherein the second pair of bypass multiplexers are configured to reduce a resolution of the ADC by one bit.
4. The ADC of claim 1 , wherein the first pair of bypass multiplexers is configured to selectively bypass one of the differential digital delay lines to set an offset for the ADC.
5. The ADC of claim 1 , wherein the ADC further comprises an out-of-range circuit, the out-of-range circuit comprising a set of delay elements included in the differential digital delay lines configured to produce data to indicate a degree to which an input to the ADC is out of an input range.
6. The ADC of claim 1 , wherein the ADC further comprises a calibration circuit, the calibration circuit comprising a set of delay elements included in the differential digital delay lines configured to calibrate a source to the differential digital delay lines.
7. The ADC of claim 1 , wherein the differential digital delay lines are configured to measure a difference between an input voltage and a reference voltage.
8. The ADC of claim 1 , further comprising a current source circuit configured to mirror reference currents to each of the differential digital delay lines.
9. The ADC of claim 1 , wherein:
the ADC further comprises a calibration circuit, the calibration circuit comprising a set of delay elements included in the differential digital delay lines configured to calibrate a source to the differential digital delay lines; and
the ADC is communicatively coupled to a current source circuit configured to mirror a plurality of reference currents to each of the differential digital delay lines, wherein the calibration circuit is configured to adjust the plurality of reference currents to minimize error.
10. The ADC of claim 1 , further comprising a transconductor configured to convert an input differential voltage to a differential current, wherein the differential digital delay lines are configured to measure the differential current and generate data representing the input differential voltage.
11. The ADC of claim 1 , further comprising a transconductor configured to:
convert an input differential voltage to a differential current; and
accept an input based on the plurality of differential digital delay lines to adjust a voltage-to-current range.
12. The ADC of claim 1 , wherein each differential digital delay line includes a chain of current limited buffers.
13. The ADC of claim 1 , wherein:
the given differential digital delay line is configured to operate at a speed according to a differential current applied to the differential digital delay line;
the ADC further comprises a latch; and
the latch is configured to save data from a slower differential digital delay line upon a completion of faster differential digital delay line.
14. The ADC of claim 1 , further comprising a delay circuit comprising a yet another set of delay elements included in the differential digital delay line, wherein the delay circuit is configured to calibrate a source to the differential digital delay lines.
15. A microcontroller comprising:
a processor core;
memory;
a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC), the ADC comprising:
differential digital delay lines comprising a plurality of series coupled delay cells, wherein a delay time of a first delay line is controlled by a first voltage at an input of the ADC and a delay time of a second delay line is controlled by a second voltage at the input of the ADC;
a first pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells;
a plurality of latches each coupled with the series coupled delay cells;
a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC; and
a plurality of logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.
16. The microcontroller of claim 15 , wherein the first pair of bypass multiplexers is placed at a 50% point of the series coupled delay cells.
17. The microcontroller of claim 15 , further comprising a second pair of bypass multiplexers placed at a 50% point between the first pair of bypass multiplexers and a delay line end, wherein the second pair of bypass multiplexers are configured to reduce a resolution of the ADC by one bit.
18. The microcontroller of claim 15 , wherein the first pair of bypass multiplexers is configured to selectively bypass one of the differential digital delay lines to set an offset for the ADC.