Method of integrating FinFET CMOS devices with embedded nonvolatile memory cells
A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.
1. A method of forming a memory device, comprising:
forming pairs of spaced apart first conductive blocks over and insulated from a first surface area of the substrate, wherein for each pair of the spaced apart first conductive blocks, an area between the first conductive blocks defines an inner region, and areas outside of the first conductive blocks define outer regions;
forming a plurality of source regions each disposed in the substrate and in one of the inner regions;
forming second conductive blocks each disposed over and insulated from one of the source regions;
forming third conductive blocks each disposed in one of the outer regions, and disposed over and insulated from the substrate;
forming a protective layer over the first, second and third conductive blocks;
after the forming of the protective layer:
performing a silicon etch in a second surface area of the substrate to form fins of the substrate, and
forming fourth conductive blocks each extending along and insulated from top and side surfaces of one of the fins of the substrate; and
after the performing of the silicon etch and the forming of the fourth conductive blocks:
removing the protective layer,
performing an etch to selectively remove a middle portion of each of the third conductive blocks,
forming a plurality of drain regions each disposed in the substrate and adjacent to one of the third conductive blocks, and
forming a second source region and a second drain region in each of the fins of the substrate.
2. The method of claim 1 , wherein for each of the fins of the substrate, the fourth conductive block is disposed between the second source region and the second drain region.
3. The method of claim 1 , wherein the forming of the second and third conductive blocks includes:
forming a layer of conductive material over the substrate; and
performing a chemical mechanical polish process to planarize a top surface of the layer of conductive material.
4. The method of claim 1 , wherein the fourth conductive blocks are insulated from the top and side surfaces of the fins of the substrate by a high K dielectric layer.
5. The method of claim 4 , wherein the fourth conductive blocks comprise a metal material.
6. The method of claim 5 , wherein the first, second and third conductive blocks comprise a polysilicon material.
7. The method of claim 1 , further comprising:
forming fifth conductive blocks over and insulated from a third surface area of the substrate; and
forming third source regions and third drain regions in the third surface area of the substrate adjacent to the fifth conductive blocks.
8. The method of claim 7 , wherein the forming of the second, third and fifth conductive blocks comprises:
forming a first oxide layer on the first surface area of the substrate;
forming a second oxide layer on the third surface area of the substrate;
forming a layer of polysilicon on the first and second oxide layers using a polysilicon deposition process;
the performing of the etch to selectively remove the middle portion of each of the third conductive blocks further includes removing selected portions of the polysilicon layer over the second oxide layer;
wherein the second oxide layer has a thickness greater than that of the first oxide layer.
9. A method of forming a memory device, comprising:
forming pairs of spaced apart first conductive blocks over and insulated from a first surface area of the substrate, wherein for each pair of the spaced apart first conductive blocks, an area between the first conductive blocks defines an inner region, and areas outside of the first conductive blocks define outer regions;
forming a plurality of source regions each disposed in the substrate and in one of the inner regions;
forming a first oxide layer on the first surface area of the substrate, and on second and third surface areas of the substrate;
removing the first oxide layer from the first surface area of the substrate;
forming a second oxide layer on the first surface area of the substrate;
forming a polysilicon layer over the first, second and third surface areas of the substrate;
planarizing a top surface of the polysilicon layer over the first surface area of the substrate, leaving first blocks of the polysilicon layer each disposed over and insulated from one of the source regions and second blocks of the polysilicon layer each disposed in one of the outer regions and on the second oxide layer;
forming a protective layer over the first conductive blocks and over the first and second blocks of the poly silicon layer;
after the forming of the protective layer:
removing the polysilicon layer and the first oxide layer from the second surface area of the substrate,
performing a silicon etch in a second surface area of the substrate to form fins of the substrate, and
forming second conductive blocks each extending along and insulated from top and side surfaces of one of the fins of the substrate;
after the performing of the silicon etch and the forming of the second conductive blocks:
removing the protective layer,
performing an etch to selectively remove a middle portion of each of the second blocks of the polysilicon, and selected portions of the polysilicon layer over the third surface area of the substrate leaving third blocks of the polysilicon,
forming a plurality of drain regions each disposed in the substrate and adjacent to one of the second blocks of polysilicon,
forming a second source region and a second drain region in each of the fins of the substrate, and
forming third source regions and third drain regions in the third surface area of the substrate adjacent to the third blocks of the polysilicon.
10. The method of claim 9 , wherein the second oxide layer has a thickness greater than that of the first oxide layer.
11. The method of claim 9 , wherein for each of the fins of the substrate, the second conductive block is disposed between the second source region and the second drain region.
12. The method of claim 9 , wherein the second conductive blocks are insulated from the top and side surfaces of the fins of the substrate by a high K dielectric layer.
13. The method of claim 12 , wherein the second conductive blocks comprise a metal material.