IP Library Granted Patent US 9,972,493
Granted Patent B2
US 9,972,493 · App. 15/594,883 · Granted May 15, 2018

Method of forming low height split gate memory cells

Inventors: Chien-Sheng Su (Saratoga, CA); Jeng-Wei Yang (Zhubei, TW); Man-Tang Wu (Xinpu Township, TW); Chun-Ming Chen (New Taipei, TW); Hieu Van Tran (San Jose, CA); Nhan Do (Saratoga, CA)
Assignee: Silicon Storage Technology, Inc.
H01L21/28G11C16/0425H01L21/28273H01L21/30604H01L29/42328H01L29/772
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Quick Facts
Patent No.
US 9,972,493
App. No.
15/594,883
Granted
May 15, 2018
Kind
B2
Abstract

A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

Claims (34)

1. A method of forming a memory device, comprising:

forming a first insulation layer on a semiconductor substrate;

forming a layer of conductive material on the first insulation layer;

forming an insulation block on the layer of conductive material;

forming an insulation spacer along a side surface of the insulation block and on the layer of conductive material;

etching the layer of conductive material to form a block of the conductive material disposed directly under the insulation block and the insulation spacer;

removing the insulation spacer, leaving exposed a portion of a top surface and an upper edge of the block of the conductive material;

forming a second insulation layer having a first portion wrapping around the exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer laterally adjacent to the block of the conductive material;

forming a conductive block having a first portion disposed over the second insulation layer second portion and the first insulation layer, and a second portion that extends up and over the block of the conductive material, wherein the conductive block first portion is laterally adjacent to and insulated from the block of the conductive material, and wherein the conductive block extends along the first portion of the second insulation layer; and

forming spaced apart source and drain regions in the semiconductor substrate, with a channel region extending there between, wherein the block of the conductive material is disposed over a first portion of the channel region and the source region, and wherein the first portion of the conductive block is disposed over a second portion of the channel region and insulated therefrom by the first insulation layer and the second insulation layer.

2. The method of claim 1 , further comprising:

oxidizing a side surface of the block of the conductive material before the forming of the second insulation layer to form a third insulation layer extending along the side surface, wherein the forming of the second insulation layer includes forming a portion of the second insulation layer extending along the third insulation layer.

3. The method of claim 2 , wherein the side surface of the block of conductive material faces the conductive block.

4. The method of claim 2 , wherein:

the second portion of the conductive block is insulated from the portion of the top surface of the block of conductive material by the second insulation layer, and not by the first insulation layer and not by the third insulation layer; and

the first portion of the conductive block is insulated from the substrate by the first insulation layer and the second insulation layer, and not by the third insulation layer.

5. The method of claim 4 , wherein the first portion of the conductive block is insulated from the block of conductive material by the second insulation layer and the third insulation layer, and not by the first insulation layer.

6. The method of claim 1 , wherein:

the second portion of the conductive block is insulated from the portion of the top surface of the block of conductive material by the second insulation layer, and not by the first insulation layer; and

the first portion of the conductive block is insulated from the substrate by the first insulation layer and the second insulation layer.

7. The method of claim 1 , wherein all insulation separating the first portion of the conductive block and the substrate is thicker than all insulation separating the second portion of the conductive block and the portion of the top surface of the block of conductive material.

8. The method of claim 1 , wherein the removing of the insulation spacer includes reducing a thickness of the first portion of the first insulation layer.

9. The method of claim 1 , further comprising:

forming spaced apart second source and second drain regions in the semiconductor substrate, with a second channel region extending there between;

forming a second conductive block over and insulated from the second channel region;

wherein a top surface of the second conductive block has a height relative to a surface of the substrate that is substantially equal to that of a top surface of the conductive block.

10. The method of claim 1 , further comprising:

forming spaced apart second source and second drain regions in the semiconductor substrate, with a second channel region extending there between;

forming a second conductive block over and insulated from the second channel region;

wherein a top surface of the second conductive block has a height relative to a surface of the substrate that is substantially equal to that of a top surface of the insulation block.

11. The method of claim 1 , further comprising:

forming spaced apart second source and second drain regions in the semiconductor substrate, with a second channel region extending there between;

forming a second conductive block over and insulated from the second channel region;

wherein a top surface of the second conductive block has a height relative to a surface of the substrate that is substantially equal to that of a top surface of the insulation block and a top surface of the conductive block.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2017
From: SU, CHIEN-SHENG; YANG, JENG-WEI; WU, MAN-TANG; CHEN, CHUN-MING; TRAN, HIEU VAN; DO, NHAN
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 044474/0503 →
Continuity (2)
Provisional Application 62372247 · Aug 8, 2016
Related Publication 20180040482A1 · Feb 8, 2018