Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected memory cell during an operation. The first voltage is greater in magnitude than the second voltage and the first voltage is applied for a shorter duration than the second voltage. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.
1. A method comprising:
providing consecutive pulses to a selected memory cell during an operation, wherein providing each pulse of the consecutive pulses comprises:
providing a first voltage to the selected memory cell;
providing a second voltage to the selected memory cell, wherein the first voltage is greater in magnitude than the second voltage, and wherein the first voltage is applied for a shorter duration than the second voltage; and
determining a state of the selected memory cell after providing the first voltage and the second voltage.
2. The method of claim 1 , comprising providing a third voltage to the selected memory cell after providing the first voltage, wherein the third voltage is less than the second voltage in magnitude.
3. The method of claim 1 , wherein the operation is a read operation, and wherein a magnitude of the second voltage is approximately 1.0 volt.
4. The method of claim 1 , wherein the operation is a verify operation, and wherein a magnitude of the second voltage is approximately 1.5 volt.
5. The method of claim 1 , wherein determining the state comprises sensing a current across the memory cell.
6. The method of claim 1 , wherein determining the state comprises sensing a data line response.
7. A method comprising:
providing a first voltage to a selected memory cell;
providing a second voltage to the selected memory cell during a verify operation, wherein the second voltage is approximately between twenty percent and thirty percent in magnitude of the first voltage, wherein the first voltage is a voltage spike, and wherein the magnitude of the first voltage is approximately 5 volts; and
determining a state of the selected memory cell after providing the first voltage and the second voltage.
8. The method of claim 7 , wherein the first voltage is provided to the selected memory cell prior to the operation.
9. The method of claim 7 , wherein the second voltage is applied longer than the first voltage is applied.
10. The method of claim 7 , wherein the second voltage is approximately 1.5 volt.
11. A method comprising:
applying a multi-level pulse to a control gate of a memory cell, wherein applying the multi-level pulse comprises:
applying a first voltage level;
transitioning the first voltage level directly to a second voltage level; and
transitioning the second voltage level to a third voltage level, wherein the first and second voltage levels are higher in magnitude than the third voltage level, and wherein the first voltage is level is applied to the control gate of the memory cell for a shorter time period than the second and third voltage levels.
12. The method of claim 11 , wherein the second voltage is a read or verify voltage and the third voltage is approximately 0 volts.
13. The method of claim 12 , wherein the second voltage is approximately 1 or 1.5 volts.
14. The method of claim 11 , wherein the third voltage is approximately 1 or 1.5 volts.
15. The method of claim 11 , wherein applying the first voltage level comprises applying an excited pulse having a magnitude of approximately 5 volts.
16. The method of claim 11 , comprising determining a state of the memory cell after applying the multi-level pulse.