Self-aligned sacrificial epitaxial capping for trench silicide
A method for forming a self-aligned sacrificial epitaxial cap for trench silicide and the resulting device are provided. Embodiments include a Si fin formed in a PFET region; a pair of Si fins formed in a NFET region; epitaxial S/D regions formed on ends of the Si fins; a replacement metal gate formed over the Si fins in the PFET and NFET regions; metal silicide trenches formed over the epitaxial S/D regions in the PFET and NEFT regions; a metal layer formed over top surfaces of the S/D region in the PFET region and top and bottom surfaces of the S/D regions in the NFET region, wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view.
1. A device comprising:
a silicon (Si) fin disposed in a p-channel field-effect transistor (PFET) region;
a pair of Si fins disposed in a n-channel field-effect transistor (NFET) region;
epitaxial source/drain (S/D) regions disposed on ends of the Si fins;
a first metal disposed on top surfaces of the S/D region in the PFET region and the first metal is disposed directly on top and bottom surfaces of the S/D regions in the NFET region; and
trenches filled with a second metal and formed over the first metal and the epitaxial S/D regions in the PFET and NFET regions,
wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view,
wherein the second metal is disposed directly on the first metal that is disposed directly on the bottom surfaces of the S/D regions in between the diamond shaped S/D regions in the NFET region in cross-sectional view, and
wherein the epitaxial source/drain (S/D) region in the PFET region comprises a boron-doped silicon germanium (SiGe).
2. The device according to claim 1 , wherein the epitaxial source/drain (S/D) regions in the NFET region comprise silicon phosphorous (SiP).
3. The device according to claim 1 , wherein the PFET region has a low contact resistance due to the boron-doped SiGe.
4. The device according to claim 1 , wherein the NFET region has low contact resistance due to increased contact area for the second metal layer.
5. A device comprising:
a fin disposed in a p-channel field-effect transistor (PFET) region;
a pair of fins disposed in a n-channel field-effect transistor (NFET) region;
epitaxial source/drain (S/D) regions disposed on ends of the Si fins;
a first metal disposed on top surfaces of the S/D region in the PFET region and the first metal is disposed directly on top and bottom surfaces of the S/D regions in the NFET region; and
trenches filled with a second metal and disposed over the first metal and the epitaxial S/D regions in the PFET and NFET regions,
wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view,
wherein the second metal is disposed directly on the first metal that is disposed directly on the bottom surfaces of the S/D regions in between the diamond shaped S/D regions in the NFET region in cross-sectional view, and
wherein the epitaxial S/D region in the PFET region comprises a boron-doped silicon germanium (SiGe).
6. The device according to claim 5 , wherein the epitaxial source/drain (S/D) regions in the NFET region comprise silicon phosphorous (SiP).
7. The device according to claim 5 , wherein the PFET region has a low contact resistance due to the boron-doped SiGe.
8. The device according to claim 5 , wherein the NFET region has low contact resistance due to increased contact area for the second metal layer.
9. A device comprising:
a silicon (Si) fin disposed in a p-channel field-effect transistor (PFET) region;
a pair of Si fins disposed in a n-channel field-effect transistor (NFET) region;
epitaxial source/drain (S/D) regions disposed on ends of the Si fins;
a first metal disposed on top surfaces of the S/D region in the PFET region and the first metal is disposed directly on top and bottom surfaces of the S/D regions in the NFET region; and
trenches filled with a second metal and disposed over the first metal and the epitaxial S/D regions in the PFET and NFET regions,
wherein the epitaxial S/D regions in the PFET and NFET regions are diamond shaped in cross-sectional view,
wherein the second metal is disposed directly on the first metal that is disposed directly on the bottom surfaces of the S/D regions in between the diamond shaped S/D regions in the NFET region in cross-sectional view,
wherein the epitaxial source/drain (S/D) region in the PFET region comprises a boron-doped silicon germanium (SiGe), and
wherein the epitaxial source/drain (S/D) regions in the NFET region comprise silicon phosphorous (SiP).
10. The device according to claim 9 , wherein the PFET region has a low contact resistance due to the boron-doped SiGe.
11. The device according to claim 9 , wherein the NFET region has low contact resistance due to increased contact area for the second metal layer.
12. The device according to claim 9 , wherein B or Ga is implanted into the epitaxial S/D region in the PFET region.