Package structure for heat dissipation

1. A method, comprising:

bonding a first surface of a plurality of first dies to a wafer, each one of the plurality of first dies being in a respective package area of the wafer;

depositing a first gap-filling material over the plurality of first dies;

thinning the plurality of first dies and first gap-filling material, thereby exposing conductive through vias at a second surface of the plurality of first dies;

bonding a second die of a plurality of second dies to each one of the plurality of first dies;

depositing a second gap-filling material over the plurality of second dies;

thinning the plurality of second dies and second gap-filling material, thereby exposing conductive through vias at a second surface of the plurality of second dies; and

singulating the first and second gap-filling material, the singulating producing a die stack comprising a first die of the plurality of first dies and a second die of the plurality of second dies.

2. The method of claim 1 ,

wherein the wafer comprises one or more active devices and one or more exposed metal features, and wherein bonding the first surface of a plurality of first dies to the wafer comprises:

aligning a metal feature in a first die of the plurality of first dies to a corresponding exposed metal feature of the wafer; and

bonding the metal feature in the first die to the corresponding exposed metal feature of the wafer,

wherein the metal feature in the first die is coupled to a conductive through via of the first die without using an eutectic material.

3. The method of claim 2 , wherein the die stack further comprises a singulated portion of the wafer.

4. The method of claim 1 , wherein the wafer is a carrier without any active devices formed therein.

5. The method of claim 4 , further comprising:

prior to singulating, attaching a backside carrier to the second surface of the plurality of second dies;

removing the wafer; and

forming a plurality of connectors on the first surface of the plurality of first dies.

6. The method of claim 1 , wherein bonding the second die comprises:

bonding a contact pad to a conductive through via; and

bonding a dielectric material of the second die to a dielectric material of the first die at an interface of the first die and second die.

7. The method of claim 1 , wherein singulating the die stack comprises plasma dicing.

8. The method of claim 1 , further comprising:

forming a logic device in a logic region of the wafer, wherein the plurality of first dies and plurality of second dies are laterally separated from the logic region; and

bonding a conductive element to metal features of the logic device, wherein the die stack includes the logic device and conductive element.

9. The method of claim 8 , wherein the conductive element comprises a stack of thermal chips having conductive vias bonded to the metal features of the logic device.

10. The method of claim 8 , wherein the conductive element comprises a thermal metal bulk bonded to the metal features of the logic device.

11. A method, comprising:

bonding a first die to a wafer;

depositing a first gap-filling material over the first die, the first gap-filling material laterally surrounding the first die;

thinning the first die and first gap-filling material to expose conductive features at a top surface of the first die;

bonding a second die the top surface of the first die;

depositing a second gap-filling material over the second die, the second gap-filling material laterally surrounding the second die;

thinning the second die and second gap-filling material to expose conductive features at a top surface of the second die; and

singulating the wafer to form a first package, the first package comprising the first die and the second die, wherein the first gap-filling material and the second gap-filling material remain on sidewalls of the first die and the second die.

12. The method of claim 11 , further comprising:

bonding a first heat dissipation feature to the wafer, the first heat dissipation feature being aligned to a logic area of the wafer, wherein the first gap-filling material surrounds the first heat dissipation feature, wherein thinning the first gap-filling material exposes a top surface of the first heat dissipation feature.

13. The method of claim 12 , further comprising:

cutting the first gap-filling material between the first die and the first heat dissipation feature to form an opening; and

depositing a thermal interface material in the opening.

14. The method of claim 13 , further comprising:

cutting trenches in the top surface of the second die; and

depositing the thermal interface material in the trenches.

15. The method of claim 11 , wherein the wafer is a carrier wafer free of active devices.

16. The method of claim 11 , wherein bonding the second die to the top surface of the first die comprises:

aligning second conductive features at a bottom surface of the second die to the conductive features of the first die; and

bonding the second conductive features of the second die to the conductive features of the first die without using a eutectic material.

17. The method of claim 16 , wherein bonding the second die to the top surface of the first die further comprises:

bonding a dielectric material at the top surface of the first die to a dielectric material at the bottom surface of the second die.

18. A method, comprising:

bonding a first heat dissipation feature to a substrate, the substrate having active devices formed therein;

depositing a first gap-filling material over the first heat dissipation feature, the first gap-filling material laterally surrounding the first heat dissipation feature;

planarizing the first gap-filling material to expose a top surface of the first heat dissipation feature;

bonding a second heat dissipation feature to the first heat dissipation feature;

depositing a second gap-filling material over the second heat dissipation feature, the second gap-filling material laterally surrounding the second heat dissipation feature;

planarizing the second gap-filling material to a top surface of the second heat dissipation feature; and

forming a first trench in the first gap-filling material between the first heat dissipation feature and an adjacent die stack, wherein the first gap-filling material remains on sidewalls of the first heat dissipation feature.

19. The method of claim 18 , further comprising:

depositing a thermal interface material in the first trench and over the second heat dissipation feature; and

attaching a heat spreader to the thermal interface material.

20. The method of claim 18 , wherein each of the first heat dissipating feature and the second heat dissipating feature comprises a thermal chip, the thermal chip comprising:

a plurality of conductive vias formed in a surrounding material, wherein each of the plurality of conductive vias traverses an entire thickness of the surrounding material.