IP Library › Granted Patent US 10,283,206

Granted Patent B2

US 10,283,206 · App. 15/792,590 · Granted May 7, 2019

High speed sensing for advanced nanometer flash memory device

Inventors: Hieu Van Tran (San Jose, CA); Anh Ly (San Jose, CA); Thuan Vu (San Jose, CA); Hung Quoc Nguyen (Fremont, CA); Vipin Tiwari (Dublin, CA)

Assignee: SILICON STORAGE TECHNOLOGY, INC.

G11C16/28 G11C7/062 G11C7/067 G11C7/12 G11C16/00 G11C16/06 G11C16/24 G11C16/26 H01L27/11519 G11C2207/063

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Quick Facts

Patent No.: US 10,283,206
App. No.: 15/792,590
Granted: May 7, 2019
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.

Claims (45)

1. A flash memory sensing circuit, comprising:

a memory data read block coupled to a selected flash memory cell and comprising a bit line, a first parasitic capacitor from a first adjacent bit line, a second parasitic capacitor from a second adjacent bit line, and a memory data read block output node;

a memory reference read block coupled to a reference memory cell and comprising a memory reference read block output node;

a precharge circuit for precharging the memory data read block output node and the memory reference read block output node to a bias voltage to compensate for the first parasitic capacitor and the second parasitic capacitor, wherein the magnitude of the bias voltage varies based on one or more of the position of the selected flash memory cell within a memory array, the bit line position of the selected flash memory cell within a memory array, or the word line position of the selected flash memory cell within a memory array; and

a differential amplifier block coupled to the memory data read block output node and the memory reference read block output node for determining a value stored in the selected flash memory cell.

2. The flash memory sensing circuit of claim 1 , wherein the memory data read block comprises a current source, a cascoding sensing NMOS transistor, a bitline clamp NMOS transistor, a diode connected sensing load PMOS transistor, and a capacitor.

3. The flash memory sensing circuit of claim 2 , wherein the memory reference read block comprises a current source, a reference bitline clamp NMOS transistor, a cascoding sensing NMOS transistor, an a diode connected sensing load PMOS transistor, and a capacitor.

4. The flash memory sensing circuit of claim 1 , wherein the differential amplifier block comprises an input differential pair of NMOS transistors, current mirror load PMOS transistors, output PMOS transistor, current bias NMOS transistor, and an output current bias NMOS transistor.

5. The flash memory sensing circuit of claim 1 , wherein the precharge control signal varies based on the position of the selected flash memory cell within a memory array.

6. The flash memory sensing circuit of claim 1 , wherein the precharge control signal varies based on the bit line position of the selected flash memory cell within a memory array.

7. The flash memory sensing circuit of claim 1 , wherein the precharge control signal varies based on the word line position of the selected flash memory cell within a memory array.

8. A flash memory sensing circuit comprising:

a bit line coupled to a selected flash memory cell;

a first parasitic capacitor coupled to the bit line and a first adjacent bit line;

a second parasitic capacitor coupled to the bit line and a second adjacent bit line;

a precharge circuit coupled to the bit line for precharging the bit line to a bias voltage wherein the magnitude of the bias voltage varies based on one or more of the position of the selected flash memory cell within a memory array, the bit line position of the selected flash memory cell within a memory array, or the word line position of the selected flash memory cell within a memory array; and

a single ended amplifier comprising a PMOS transistor and an NMOS transistor, wherein a gate of the PMOS transistor is coupled to the bit line and an output of the amplifier indicates the value stored in the selected flash memory cell.

9. The flash memory sensing circuit of claim 8 , wherein the output is generated without the use of a reference memory cell.

10. The flash memory sensing circuit of claim 8 , wherein the magnitude of the bias voltage varies based on the position of the selected flash memory cell within a memory array.

11. The flash memory sensing circuit of claim 10 , wherein the magnitude of the bias voltage varies based on the bit line position of the selected flash memory cell within a memory array.

12. The flash memory sensing circuit of claim 10 , wherein the magnitude of the bias voltage varies based on the word line position of the selected flash memory cell within a memory array.

13. The flash memory sensing circuit of claim 8 , wherein a bulk of the PMOS transistor is forward biased.

14. The flash memory sensing circuit of claim 8 , wherein the precharge circuit comprises a bit line capacitor coupled to the bit line for storing a precharge voltage.

15. The flash memory sensing circuit of claim 9 , wherein the precharge circuit comprises a PMOS transistor coupled to a voltage source and the bit line and controlled by a precharge control signal.

16. The flash memory sensing circuit of the claim 14 , wherein the magnitude of the precharge voltage varies based on the position of the selected flash memory cell within a memory array.

17. The flash memory sensing circuit of claim 16 , wherein the magnitude of the precharge voltage varies based on the bit line position of the selected flash memory cell within a memory array.

18. The flash memory sensing circuit of claim 16 , wherein the magnitude of the precharge voltage varies based on the word line position of the selected flash memory cell within a memory array.

19. The flash memory sensing circuit of the claim 15 , wherein the precharge control signal varies based on the position of the selected flash memory cell within a memory array.

20. The flash memory sensing circuit of claim 19 , wherein the precharge control signal varies based on the bit line position of the selected flash memory cell within a memory array.

21. The flash memory sensing circuit of claim 19 , wherein the precharge control signal varies based on the word line position of the selected flash memory cell within a memory array.

22. A flash memory sensing circuit comprising:

a selected bit line coupled to a flash memory cell;

a first parasitic capacitor coupled to the selected bit line and a first adjacent bit line;

a second parasitic capacitor coupled to the bit line and a second adjacent bit line;

a reference line coupled to a reference memory cell;

a third parasitic capacitor coupled to the reference line and a third adjacent bit line;

a fourth parasitic capacitor coupled to the reference line and a fourth adjacent bit line; and

a differential amplifier coupled to the selected bit line and the reference line for determining a value stored in the selected flash memory cell;

wherein the selected bit line and the reference line are coupled to a precharge circuit to compensate for the first parasitic capacitor, the second parasitic capacitor, the third parasitic capacitor, and the fourth parasitic capacitor, wherein the magnitude of the bias voltage varies based on one or more of the position of the selected flash memory cell within a memory array, the bit line position of the selected flash memory cell within a memory array, or the word line position of the selected flash memory cell within a memory array.

23. The flash memory sensing circuit of claim 22 , wherein the precharge circuit comprises a bit line capacitor coupled to the selected bit line for storing a precharge voltage and a reference line capacitor coupled to the reference line for storing a precharge voltage.

24. The flash memory sensing circuit of claim 23 , wherein the precharge circuit comprises a PMOS transistor coupled to a voltage source and the selected bit line and controlled by a precharge control signal.

25. The flash memory sensing circuit of claim 24 , wherein the precharge control signal varies based on the position of the selected flash memory cell within a memory array.

26. The flash memory sensing circuit of claim 25 , wherein the precharge control signal varies based on the bit line position of the selected flash memory cell within a memory array.

27. The flash memory sensing circuit of claim 25 , wherein the precharge control signal varies based on the word line position of the selected flash memory cell within a memory array.

28. The flash memory sensing circuit of claim 25 , wherein a bulk of the PMOS transistor is forward biased.

Assignments (12)

RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022

From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT