IP Library Granted Patent US 10,651,126
Granted Patent B2
US 10,651,126 · App. 15/835,909 · Granted May 12, 2020

Methods and apparatus for wafer-level die bridge

Inventors: Chien-Kang Hsiung (Taipei, TW); Arvind Sundarrajan (Singapore, SG)
Assignee: APPLIED MATERIALS, INC.
H01L23/5386H01L21/76802H01L21/76829H01L22/14H01L23/3128H01L23/5384H01L24/94H01L25/0655H01L24/16H01L24/17H01L24/81H01L24/83H01L25/10H01L2224/04105H01L2224/058H01L2224/0579H01L2224/05639H01L2224/05647H01L2224/05684H01L2224/16145H01L2224/16235H01L2224/18H01L2224/2919H01L2224/32225
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Quick Facts
Patent No.
US 10,651,126
App. No.
15/835,909
Granted
May 12, 2020
Kind
B2
Abstract

A wafer-level bridge die is affixed with an adhesive layer to a redistribution layer (RDL) that has been temporarily bonded to a carrier. Electrical interconnects are formed on the RDL and on the bridge die and encapsulated in a first mold layer. A plurality of dies are coupled to the RDL and the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die. A second mold layer is formed on the first mold layer to encapsulate the plurality of dies. The temporary bond is then broken and the carrier is removed, exposing the RDL connections.

Claims (37)

1. A method of forming a wafer level bridge die, comprising:

forming a redistribution layer (RDL);

affixing a bridge die on the RDL, the bridge die having electrical connections on an exposed surface opposite of the RDL;

forming at least one electrical interconnect on the RDL;

forming at least one electrical interconnect on the bridge die;

forming at least one first portion of at least one through mold via (TMV) on the RDL;

forming a first mold layer over the RDL and the bridge die;

forming at least one second portion of the at least one TMV;

coupling a plurality of dies to the RDL and to the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die; and

forming a second mold layer on the first mold layer and on the plurality of dies, the at least one TMV having an electrical connection at a top surface of the second mold layer for supporting package-on-package (PoP) electrical connections.

2. The method of claim 1 , further comprising:

forming the at least one TMV using an electroplating process.

3. The method of claim 1 , further comprising:

forming the RDL on a carrier.

4. The method of claim 1 , further comprising:

affixing the bridge die on the RDL using an adhesive between the bridge die and the RDL.

5. The method of claim 1 , further comprising:

forming at least one integrated passive device on the first mold layer; and

forming the second mold layer on the at least one integrated passive device.

6. The method of claim 1 , further comprising:

using a copper-based material to form at least one electrical interconnect on the RDL or at least one electrical interconnect on the bridge die.

7. A method of forming a wafer level bridge die, comprising:

temporarily bonding a redistribution layer (RDL) on a carrier;

affixing a bridge die on the RDL, the bridge die having electrical connections on an exposed surface opposite of the RDL;

forming at least one electrical interconnect on the RDL;

forming at least one electrical interconnect on the exposed surface of the bridge die;

forming a first mold layer on the RDL and the bridge die;

coupling a plurality of dies to the RDL and to the bridge die such that a die is electrically connected to at least one electrical interconnect of the RDL and to at least one electrical interconnect of the bridge die;

forming a second mold layer on the first mold layer and on the plurality of dies;

removing the carrier from the RDL; and

forming at least one through mold via from the RDL to a top surface of the second mold layer.

8. The method of claim 7 , further comprising:

affixing a thermal exchange layer to a top surface of at least one of the plurality of dies.

9. The method of claim 7 , further comprising:

electrically connecting the RDL to a substrate or printed circuit board.

10. The method of claim 7 , further comprising:

forming at least one integrated passive device on the first mold layer before forming the second mold layer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2018
From: APPLIED MATERIALS SINGAPORE TECHNOLOGY PTE. LTD.
To: APPLIED MATERIALS, INC.
Reel/Frame 046004/0631 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2018
From: HSIUNG, CHIEN-KANG
To: APPLIED MATERIALS, INC.
Reel/Frame 044801/0404 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2018
From: SUNDARRAJAN, ARVIND
To: APPLIED MATERIALS SINGAPORE TECHNOLOGY PTE. LTD.
Reel/Frame 044730/0008 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2018
From: HSIUNG, CHIEN-KANG; SUNDARRAJAN, ARVIND
To: APPLIED MATERIALS, INC.
Reel/Frame 044533/0080 →
Continuity (1)
Related Publication 20190181092A1 · Jun 13, 2019
Cited By (3)
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