IP Library › Granted Patent US 10,461,118
Granted Patent B2
US 10,461,118 · App. 15/843,121 · Granted Oct 29, 2019

Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk

Inventors: Yi-Ann Chen (Campbell, CA); Abid Husain (San Jose, CA); Hideki Takeuchi (San Jose, CA)
Assignee: ATOMERA INCORPORATED
H01L27/14689H01L27/1463H01L27/14621H01L27/14627H01L27/14645H01L27/14685H01L31/035236H01L31/109
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,461,118
App. No.
15/843,121
Granted
Oct 29, 2019
Kind
B2
Abstract

A method for making a CMOS image sensor may include forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity types by forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, forming a first well around a periphery of the retrograde well also having the second conductivity type, and forming a second well within the retrograde well having the first conductivity type. Furthermore, first and second superlattices may be respectively formed overlying each of the first and second wells, with each of the first and second superlattices comprising a plurality of stacked groups of layers, and each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Claims (37)

1. A method for making a CMOS image sensor comprising:

forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity type by

forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,

forming a first well around a periphery of the retrograde well also having the second conductivity type,

forming a second well within the retrograde well having the first conductivity type, and

forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The method of claim 1 wherein the first well defines a ring, and wherein the second well is within the ring.

3. The method of claim 1 wherein forming the second well comprises forming a lower portion and an upper portion, the upper portion having a higher dopant concentration than the lower portion.

4. The method of claim 1 further comprising forming a shallow trench isolation (STI) region between the first and second wells.

5. The method of claim 1 further comprising forming a respective shallow trench isolation (STI) region between laterally adjacent photodiodes.

6. The method of claim 1 further comprising forming a respective microlens overlying each of the photodiodes.

7. The method of claim 1 further comprising forming a respective color lens overlying each of the photodiodes.

8. The method of claim 1 wherein the first and second superlattices each further comprises a semiconductor cap layer thereon.

9. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

10. The method of claim 1 wherein the semiconductor monolayers comprise silicon.

11. A method for making a CMOS image sensor comprising:

forming a plurality of laterally adjacent photodiodes on a semiconductor substrate having a first conductivity type by

forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,

forming a first well around a periphery of the retrograde well also having the second conductivity type,

forming a second well within the retrograde well having the first conductivity type, and

forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

forming a respective color lens overlying each of the photodiodes; and

forming a respective microlens overlying each of the color lenses.

12. The method of claim 11 wherein the first well defines a ring, and wherein the second well is within the ring.

13. The method of claim 11 wherein forming the second well comprises forming a lower portion and an upper portion, the upper portion having a higher dopant concentration than the lower portion.

14. The method of claim 11 further comprising forming a shallow trench isolation (STI) region between the first and second wells.

15. A method for making a CMOS image sensor comprising:

forming a plurality of laterally adjacent photodiodes on a semiconductor substrate by

forming a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type,

forming a first well around a periphery of the retrograde well also having the second conductivity type,

forming a second well within the retrograde well having the first conductivity type, and

forming first and second superlattices respectively overlying each of the first and second wells, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.

16. The method of claim 15 wherein the first well defines a ring, and wherein the second well is within the ring.

17. The method of claim 15 wherein forming the second well comprises forming a lower portion and an upper portion, the upper portion having a higher dopant concentration than the lower portion.

18. The method of claim 15 further comprising forming a shallow trench isolation (STI) region between the first and second wells.

19. The method of claim 15 further comprising forming a respective microlens overlying each of the photodiodes.

20. The method of claim 15 further comprising forming a respective color lens overlying each of the photodiodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2017
From: CHEN, YI-ANN; HUSAIN, ABID; TAKEUCHI, HIDEKI
To: ATOMERA INCORPORATED
Reel/Frame 044950/0139 →
Continuity (1)
Related Publication 20190189676A1 · Jun 20, 2019
Cited By (20)
US 12,191,160 US 12,199,148 US 12,199,180 US 12,230,694 US 12,267,996 US 12,308,229 US 12,315,722 US 12,315,723 US 12,322,594 US 12,382,689 US 12,417,912 US 12,439,618 US 12,439,658 US 12,477,798 US 12,575,199 US 12,635,122 US 12,635,155 US 12,635,271 US 12,707,690 US 12,712,011