Stacked dies and dummy components for improved thermal performance
Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.
1. A semiconductor chip device, comprising:
a first semiconductor chip;
a second semiconductor chip stacked on the first semiconductor chip;
a first insulating bonding layer positioned between the first semiconductor chip and the second semiconductor chip and bonding the first semiconductor chip to the second semiconductor chip, the first insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer;
plural interconnects between and electrically connecting the first semiconductor chip and the second semiconductor chip;
a first dummy component stacked on the first semiconductor chip and separated from the second semiconductor chip by a first gap;
a second insulating bonding layer positioned between the first dummy component and the first semiconductor chip and bonding the first dummy component to the first semiconductor chip, the second insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; and
an inorganic insulating layer in the first gap.
2. The semiconductor chip device of claim 1 , comprising a second dummy component stacked on the first semiconductor chip and separated from the second semiconductor chip by a second gap, another inorganic insulating layer in the second gap, and a third insulating bonding layer positioned between the second dummy component and the first semiconductor chip and bonding the second dummy component to the first semiconductor chip, the third insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer.
3. The semiconductor chip device of claim 1 , comprising wherein the first inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx.
4. The semiconductor chip device of claim 1 , wherein the inorganic insulating layer and the another inorganic insulating layer comprise a SiOx inner core lined with silicon oxynitride.
5. The semiconductor chip device of claim 1 , wherein the interconnects comprise a copper pad metallurgically bonded to a through-chip-via.
6. The semiconductor chip device of claim 2 , wherein the first dummy component comprises plural dummy chips stacked together and the second dummy component comprises plural dummy chips stacked together.
7. The semiconductor chip device of claim 2 , wherein the first semiconductor chip having a floor plan with a high heat producing area and a low heat producing area, the second semiconductor chip being stacked on the low heat producing area and the first dummy component and the second dummy component being stacked on the high heat producing area.
8. The semiconductor chip device of claim 7 , wherein the high heat producing area comprises at least one processor core.
9. The semiconductor chip device of claim 2 , wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge.
10. A semiconductor chip device, comprising:
a stack of plural semiconductor chips, each two adjacent semiconductor chips of the stack of plural semiconductor chips being electrically connected by plural interconnects and physically connected by a first insulating bonding layer, the first insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer;
a first stack of dummy chips positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap, each two adjacent of the first stack of dummy chips being physically connected by a second insulating bonding layer, the second insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer;
a second stack of dummy chips positioned opposite a second side of the stack of semiconductor chips and separated from the stack of plural semiconductor chips by a second gap, each two adjacent of the second stack of dummy chips being physically connected by a third insulating bonding layer, the third insulating bonding layer including a first insulating layer and a second insulating layer bonded to the first insulating layer; and
an insulating layer in the first gap and another insulating layer in the second gap.
11. The semiconductor chip device of claim 10 , comprising another semiconductor chip, the stack of semiconductor chips being positioned on the another semiconductor chip.
12. The semiconductor chip device of claim 11 , wherein the another semiconductor chip having a floor plan with a high heat producing area and a low heat producing area, the stack of semiconductor chips being stacked on the low heat producing area and the first stack of dummy chips and the second stack of dummy chips being stacked on the high heat producing area.
13. The semiconductor chip device of claim 11 , wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge.
14. The semiconductor chip device of claim 10 , comprising wherein the first insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx.
15. The semiconductor chip device of claim 10 , wherein the insulating layer and the another insulating layer comprise a SiOx inner core lined with silicon oxynitride.
16. The semiconductor chip device of claim 10 , wherein the interconnects comprise a copper pad metallurgically bonded to a through-chip-via.
17. A method of manufacturing, comprising:
stacking a second semiconductor chip on a first semiconductor chip;
forming a first insulating bonding layer between the first semiconductor chip and the second semiconductor chip bonding the first semiconductor chip to the second semiconductor chip, the first insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer;
forming plural interconnects between and electrically connecting the first semiconductor chip and the second semiconductor chip;
stacking a first dummy component on the first semiconductor chip and separated from the second semiconductor chip by a first gap;
forming a second insulating bonding layer between the first dummy component and the first semiconductor chip and bonding the first dummy component to the first semiconductor chip, the second insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer; and
forming an inorganic insulating layer in the first gap.
18. The method of claim 17 , comprising stacking a second dummy component on the first semiconductor chip and separated from the second semiconductor chip by a second gap and, forming a third insulating bonding layer between the second dummy component and the first semiconductor chip and bonding the second dummy component to the first semiconductor chip, the third insulating bonding layer including a first inorganic insulating layer and a second inorganic insulating layer bonded to the first inorganic insulating layer, and forming another inorganic insulating layer in the second gap.
19. The method of claim 17 , wherein the first inorganic insulating layer of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises silicon oxynitride and the second inorganic insulating layer of the of the first insulating bonding layer, the second insulating bonding layer and the third insulating bonding layer comprises SiOx.
20. The method of claim 17 , wherein the inorganic insulating layer and the another inorganic insulating layer comprise a SiOx inner core lined with silicon oxynitride.
21. The method of claim 18 , wherein the first dummy component comprises plural dummy chips stacked together and the second dummy component comprises plural dummy chips stacked together.
22. The method of claim 18 , wherein the second semiconductor chip comprises a first edge and a second and opposite edge, the first dummy component having an outer edge substantially coterminous with the first edge and the second dummy component having an outer edge substantially coterminous with the second edge.