Substrate structures and methods of manufacture
A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.
1. A method of forming a substrate for a power electronic, comprising:
coupling a first dielectric layer to a first side of a ceramic layer;
coupling a second dielectric layer to a second side of the ceramic layer opposite the first side of the ceramic layer;
partially etching a first surface of a copper layer to form a pattern comprising a first thickness and a second thickness greater than the first thickness, the first thickness and the second thickness both measured perpendicular to a second surface of the copper layer opposite the first surface of the copper layer;
coupling the first surface of the copper layer with the first dielectric layer;
coupling the second dielectric layer to a metallic baseplate; and
forming traces in the copper layer by etching through the copper layer at the first thickness and etching through the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first dielectric layer.
2. The method of claim 1 , further comprising forming bonding patterns in one of the first dielectric layer, the second dielectric layer, or both the first dielectric layer and the second dielectric layer.
3. The method of claim 2 , wherein the bonding pattern comprises one of bonding ridges, conical projections, or pyramidal projections.
4. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer comprise one of an epoxy or a resin.
5. The method of claim 1 , wherein the first dielectric layer and the second dielectric layer are between 25-300 micrometers thick.
6. The method of claim 1 , wherein forming the pattern further comprises forming a third thickness different in magnitude from the first thickness and the second thickness, the third thickness measured perpendicular to the first dielectric layer.
7. The method of claim 1 , further comprising plating a layer of nickel onto a second surface of the copper layer opposite the first surface of the copper layer, and wherein forming the traces in the copper layer further comprises etching through the layer of nickel.
8. The method of claim 1 , wherein the partially etching through the copper layer at the first thickness and through the copper layer at the second thickness further comprises:
coupling a first layer of photoresist to a second surface of the copper layer;
forming a pattern in the first layer of photoresist;
etching through the copper layer at the first thickness at spaces in the pattern in the first layer of photoresist;
removing the first layer of photoresist;
coupling a second layer of photoresist to the second surface of the copper layer;
forming a pattern in the second layer of photoresist;
etching through the copper layer at the second thickness at the spaces in the pattern in the second layer of photoresist; and
removing the second layer of photoresist.
9. The method of claim 1 , further comprising laminating the traces in the copper layer with a third dielectric layer, coupling a second copper layer to the third dielectric layer, and forming traces in the second copper layer to form a stacked insulated metal substrate (IMS) for a power electronic.
10. The method of claim 1 , wherein one of the first dielectric layer, the second dielectric layer, or both the first dielectric layer and the second dielectric layer are laminated to the ceramic layer.