Partially de-centralized latch management architectures for storage devices
A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.
1. A memory system comprising:
a controller;
non-volatile memory coupled with the controller, wherein the non-volatile memory further comprises:
a non-volatile memory array comprising a plurality of dies;
latches that are located on the dies; and
latch management circuitry that dynamically identifies any one of the plurality dies as a leader die, wherein:
any of the plurality of dies can be identified as the leader die, and
the leader die performs a data transfer to or from one or more latches from one of the dies.
2. The memory system of claim 1 , wherein the data transfer comprises writing to the one or more latches when the leader die detects a write operation.
3. The memory system of claim 1 , wherein the data transfer comprises reading from the one or more latches when the leader die detects a read operation.
4. The memory system of claim 1 , wherein the leader die sends a busy signal to the controller for the data transfer.
5. The memory system of claim 1 , wherein the latch management circuitry utilizes a suspend and resume commands, wherein a partial release command results in a faster bus response and a full release command results in a slower bus response.
6. The memory system of claim 1 , wherein the leader die is one of a plurality of the die that are connected to a same bus or channel and the leader die is a leader for each of the die connected to the same bus or channel.
7. The memory system of claim 1 , wherein the non-volatile memory further comprises:
a first memory bus connecting at least a portion of the dies;
a second memory bus connecting at least a different portion of the dies; and
a bridge connecting the first memory bus and the second memory bus.
8. The memory system of claim 7 , wherein the leader die is a leader of both the at least a portion of the dies, and the at least a different portion of the dies.
9. The memory system of claim 7 , wherein transactions are run in parallel for the portion of the dies and for the different portion of the dies.
10. The memory system of claim 1 , wherein the non-volatile memory further comprises:
a first memory bus connecting at least a portion of the dies;
a second memory bus connecting at least a different portion of the dies;
a first bridge coupled with the first memory bus; and
a second bridge coupled with the second memory bus, wherein the first bridge and the second bridge are connected.
11. The memory system of claim 10 , wherein the leader die is a leader of the at least a portion of the dies, and a second leader die from the at least a different portion of the dies is a leader of the at least a different portion of the dies.
12. The memory system of claim 10 , wherein transactions are run in parallel for the portion of the dies and for the different portion of the dies.
13. The memory system of claim 1 , wherein the leader die is loaded with a sequence of operations that the leader die can run.
14. The memory system of claim 13 , wherein the sequence of operations comprises a garbage collection operation between different die located on a same bus that is managed by the leader die without the controller.
15. The memory system of claim 1 , wherein the identification of the leader die is caused by an external event or is caused by the controller.
16. A memory system comprising:
a controller;
a non-volatile memory coupled with the controller, the non-volatile memory comprising:
a plurality of memory dies,
wherein each of the memory dies comprises: cache storage for storing data, and
any one of the memory dies can be dynamically identified as a leader die; and
caching logic circuitry configured to be used by the leader die to:
manage a subset of the cache storage for a subset of the memory dies, wherein the subset of the memory dies are connected with the leader die, and
dynamically identify a cache storage of the subset of the cache storage to use for a data transfer, wherein any cache storage of the subset of the cache storage can be chosen for data transfer.
17. The memory system of claim 16 , wherein each of the cache storage comprises latches and the data transfer comprises:
writing to the latches from the subset of the memory dies when the leader die detects a write operation, and
reading from the latches from the subset of the memory dies when the leader die detects a read operation.
18. The memory system of claim 16 , wherein the subset of the memory dies comprises all dies connected to a same bus or channel and the leader die is connected to the same bus or channel.
19. The memory system of claim 16 , wherein the subset of the memory dies comprises:
a first group of dies and a second group of dies, the second group of dies separate from the first group of dies;
a first memory bus connecting the first group of dies;
a second memory bus connecting the second group of dies; and
a bridge connecting the first memory bus and the second memory bus, wherein the leader die is a leader of both the first group of dies and the second group of dies.
20. The memory system of claim 16 , wherein the subset of the memory dies comprises:
a first group of dies and a second group of dies, the second group of dies separate from the first group of dies;
a first memory bus connecting the first group of dies;
a second memory bus connecting the second group of dies;
a first bridge coupled with the first memory bus; and
a second bridge coupled with the second memory bus, wherein the first bridge and the second bridge are connected, wherein the leader die is a leader of both the first group of dies and the second group of dies.
21. The memory system of claim 16 , wherein the leader die includes a sequencer for completing a sequence of operations.
22. A memory device with a controller and NAND memory, the device comprising:
means for dynamically identifying any one of a plurality of dies in the NAND memory as a leader die, wherein any of the plurality of dies can be identified as the leader die;
means for receiving a command that includes a data transfer to or from one or more latches of the plurality of dies in the NAND memory; and
means for the leader die to manage the data transfer.