Three-dimensional memory device containing hydrogen diffusion blocking structures and method of making the same

1. A semiconductor structure, comprising:

semiconductor devices;

a silicon nitride diffusion barrier layer overlying the semiconductor devices; and

an interconnect structure extending through the silicon nitride diffusion barrier layer, wherein the interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure;

wherein: the semiconductor devices are located on a semiconductor substrate;

a first dielectric material layer overlies a portion of the semiconductor devices and embeds at least portions of first metal interconnect structures;

the silicon nitride diffusion barrier layer overlies the first dielectric material layer and includes a set of openings therein;

the titanium diffusion barrier structure comprises a set of titanium plates filling the set of openings, wherein the silicon nitride diffusion barrier layer and the set of titanium plates complimentarily provide a continuous structure extending over the semiconductor substrate, and wherein a conductive structure embedded in the first dielectric material layer contacts a titanium plate among the set of titanium plates, and the conductive structure comprises a component of the semiconductor devices or one of the first metal interconnect structures; and

the interconnect structure comprises second metal interconnect structures embedded within a second dielectric material layer overlying the silicon nitride diffusion barrier layer, wherein one of the second metal interconnect structures contacts a top surface of the titanium plate among the set of titanium plates.

2. The semiconductor structure of claim 1 , wherein:

the set of titanium plates has a first uniform thickness;

the silicon nitride diffusion barrier layer has the first uniform thickness;

a planar top surface of each titanium plate within the set of titanium plates is within a horizontal plane containing a top surface of the silicon nitride diffusion barrier layer; and

a planar bottom surface of each titanium plate within the set of titanium plates is with another horizontal plane containing a bottom surface of the silicon nitride diffusion barrier layer.

3. The semiconductor structure of claim 1 , wherein each titanium plate among the set of titanium plates consists essentially of titanium.

4. The semiconductor structure of claim 1 , wherein:

a portion of a bottom surface of a titanium plate among the set of titanium plates directly contacts the first dielectric material layer;

a portion of a top surface of the titanium plate among the set of titanium plates directly contacts the second dielectric material layer; and

an entire periphery of a bottom surface of the one of the second metal interconnect structures contacts another portion of the top surface of the titanium plate.

5. The semiconductor structure of claim 1 , wherein:

the conductive structure comprises one of the first metal interconnect structures;

a bottom surface of the first dielectric material layer is more distal from the semiconductor substrate than a topmost surface of the semiconductor devices is from the semiconductor substrate; and

the one of the second metal interconnect structures comprises a via structure.

6. The semiconductor structure of claim 1 , wherein:

the conductive structure comprises a gate electrode of a field effect transistor;

the first dielectric material layer comprises a material selected from an undoped silicate glass, a doped silicate glass, and an organosilicate glass, and laterally surrounds the gate electrode; and

the one of the second metal interconnect structures comprises a via structure.

7. The semiconductor structure of claim 6 , wherein the silicon nitride diffusion barrier layer contacts a planar top surface of a dielectric gate spacer that laterally surrounds the gate electrode.

8. The semiconductor structure of claim 1 , further comprising:

an additional silicon nitride diffusion barrier layer overlying the second dielectric material layer and including a set of additional openings therein;

a set of additional titanium plates filling the set of additional openings, wherein the additional silicon nitride diffusion barrier layer and the set of additional titanium plates complimentarily provide an additional continuous hydrogen diffusion barrier structure extending over the continuous hydrogen diffusion barrier structure, and another one of the second metal interconnect structures contacts an additional titanium plate among the set of additional titanium plates; and

third metal interconnect structures embedded within a third dielectric material layer overlying the additional silicon nitride diffusion barrier layer, wherein one of the third metal interconnect structures contacts a top surface of the additional titanium plate among the set of additional titanium plates.

9. The semiconductor structure of claim 1 , further comprising a three-dimensional NAND memory array located over the second dielectric material layer, wherein the semiconductor devices comprise a driver circuit of the three-dimensional NAND memory array.