3D semiconductor device and structure

1. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one first metal layer interconnecting said plurality of first transistors,

wherein said interconnecting comprises forming a plurality of logic gates;

a plurality of second transistors atop said first single crystal layer;

a second metal layer above said plurality of second transistors;

a plurality of third transistors atop said second transistors;

a third metal layer above said plurality of third transistors; and

a connective metal path between said third metal layer and at least one of said first transistors,

wherein at least one of said plurality of third transistors is aligned to at least one of said plurality of first transistors with less than 40 nm alignment error,

wherein said first metal layer is powered by a first voltage and said second metal layer is powered by a second voltage,

wherein said second voltage is greater than two times higher than said first voltage,

wherein said metal path comprises a through layer via,

wherein at least one of said plurality of second transistors comprises a first source, a first channel and a first drain,

wherein said first source, said first channel and said first drain have the same dopant type,

wherein said through layer via comprises a material and a majority of said material comprises tungsten,

wherein at least one of said plurality of third transistors comprises a second source, a second channel and a second drain,

wherein said second source, said second channel and said second drain have the same dopant type,

wherein a memory cell comprises at least one of said plurality of third transistors, and

wherein said memory cell is atop at least one of said of said plurality of logic gates.

2. The 3D semiconductor device according to claim 1 ,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors.

3. The 3D semiconductor device according to claim 1 ,

wherein at least one of said plurality of second transistors comprises polysilicon.

4. The 3D semiconductor device according to claim 1 ,

wherein said plurality of logic gates comprise memory periphery circuits, said memory periphery circuits comprise control of said memory cell.

5. The 3D semiconductor device according to claim 1 , further comprising:

a first plurality of external connections below said first single crystal layer,

wherein said first plurality of external connections comprises connections from said device to a first external device; and

a second plurality of external connections above said second metal layer,

wherein said second plurality of external connections comprises connections from said device to a second external device, and

wherein said first plurality of external connections comprises a through silicon via (TSV).

6. The 3D semiconductor device according to claim 1 ,

wherein at least one of said plurality of second transistors comprises a gate all around structure, and

wherein formation of said gate all around structure comprises Atomic Layer Deposition (ALD).

7. The 3D semiconductor device according to claim 1 ,

wherein fabrication processing of said device comprises first processing said first transistors followed by processing said second transistors and said third transistors above said first transistors, and

wherein said processing said first transistors accounts for the temperature associated with said processing said second transistors and said processing said third transistors by adjusting the process thermal budget of said first transistors accordingly.

8. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one first metal layer interconnecting said first transistors,

wherein said interconnecting comprises forming a plurality of logic gates;

a plurality of second transistors atop said first single crystal layer;

a second metal layer above said second transistors;

a plurality of third transistors atop said second transistors;

a third metal layer above said third transistors; and

a connective metal path between said third metal layer and at least one of said first transistors,

wherein said third transistors are aligned to said first transistors with less than 40 nm alignment error,

wherein said first metal layer is powered by a first voltage and said second metal layer is powered by a second voltage,

wherein said second voltage is greater than two times higher than said first voltage,

wherein said metal path comprises a through layer via,

wherein at least one of said second transistors comprises a first source, a first channel and a first drain,

wherein said first source, said first channel and said first drain have the same dopant type,

wherein said through layer via comprises a material and a majority of said material comprises tungsten, and

wherein a memory cell comprises at least one of said third transistors.

9. The 3D semiconductor device according to claim 8 ,

wherein a NAND type memory cell comprises at least one of said plurality of second transistors.

10. The 3D semiconductor device according to claim 8 ,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors.

11. The 3D semiconductor device according to claim 8 ,

wherein at least one of said plurality of second transistors comprises polysilicon.

12. The 3D semiconductor device according to claim 8 ,

wherein fabrication processing of said device comprises first processing said first transistors followed by processing said second transistors and said third transistors above said first transistors, and

wherein said processing said first transistors accounts for the temperature associated with said processing said second transistors and said processing said third transistors by adjusting the process thermal budget of said first transistors accordingly.

13. The 3D semiconductor device according to claim 8 ,

wherein said plurality of logic gates comprise memory periphery circuits, said memory periphery circuits comprise control of at least said memory cell.

14. The 3D semiconductor device according to claim 8 , further comprising:

a first plurality of external connections below said first single crystal layer,

wherein said first plurality of external connections comprises connections from said device to a first external device; and

a second plurality of external connections above said second metal layer,

wherein said second plurality of external connections comprises connections from said device to a second external device, and

wherein said first plurality of external connections comprises a through silicon via (TSV).

15. A 3D semiconductor device, the device comprising:

a first single crystal layer comprising a plurality of first transistors;

at least one first metal layer interconnecting said plurality of first transistors,

wherein said interconnecting comprises forming a plurality of logic gates;

a plurality of second transistors atop said first single crystal layer;

a second metal layer above said plurality of second transistors;

a plurality of third transistors atop said second transistors;

a third metal layer above said plurality of third transistors; and

a connective metal path between said third metal layer and at least one of said first transistors,

wherein at least one of said plurality of third transistors is aligned to at least one of said plurality of first transistors with less than 40 nm alignment error,

wherein said first metal layer is powered by a first voltage and said second metal layer is powered by a second voltage,

wherein said second voltage is greater than two times higher than said first voltage,

wherein said metal path comprises a through layer via, and

wherein said through layer via comprises a material and a majority of said material comprises tungsten.

16. The 3D semiconductor device according to claim 15

wherein at least one of said plurality of third transistors comprises polysilicon.

17. The 3D semiconductor device according to claim 15 ,

wherein at least one of said plurality of third transistors comprises a source, a channel and a drain, and

wherein said source, said channel and said drain have the same dopant type.

18. The 3D semiconductor device according to claim 15 ,

wherein said second transistor is a part of NAND type memory cell.

19. The 3D semiconductor device according to claim 15 ,

wherein at least one of said plurality of second transistors is self-aligned to at least one of said plurality of third transistors.

20. The 3D semiconductor device according to claim 15 ,

wherein a memory cell comprises at least one of said plurality of third transistors.