Decoders for analog neural memory in deep learning artificial neural network
Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
1. An analog neuromorphic memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each column is connected to a bit line and each memory cell comprises a word line terminal and a source line terminal;
a word line decoder circuit coupled to the word line terminals of the non-volatile memory cells through word lines, wherein the word line decoder circuit is capable of applying a low voltage or a high voltage to coupled word line terminals, and wherein the word lines are parallel to the bit lines; and
a source line decoder circuit coupled to the source line terminals of the non-volatile memory cells through source lines, wherein the source line decoder circuit is capable of applying a low voltage or a high voltage to coupled source line terminals, and wherein the source lines are perpendicular to the bit lines and the word lines.
2. The system of claim 1 , wherein each memory cell further comprises an erase gate terminal, the system further comprising:
an erase gate decoder circuit coupled to the erase gate terminals of the non-volatile memory cells, wherein the erase gate decoder circuit is capable of applying a low voltage or a high voltage to coupled erase gate terminals.
3. An analog neuromorphic memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each column is connected to a bit line and each memory cell comprises a word line terminal and a source line terminal;
a word line decoder circuit coupled to the word line terminals of the non-volatile memory cells through word lines, wherein the word lines are parallel to the bit lines, and wherein the word line decoder circuit is capable of applying a low voltage through a low voltage transistor or a high voltage through a high voltage transistor to coupled word line terminals, the word line decoder circuit comprising an isolation transistor coupled to each word line to isolate the high voltage transistor from the low voltage transistor.
4. The system of claim 3 , wherein a negative bias is applied to the word lines of each unselected memory cell during a program-and-verify operation or a read operation.
5. The system of claim 3 , wherein each of the non-volatile memory cells is a split-gate flash memory cell.
6. The system of claim 3 , wherein each of the non-volatile memory cells is a stacked-gate flash memory cell.
7. The system of claim 3 , wherein each of the non-volatile memory cells are configured to operate in a sub-threshold region.
8. The system of claim 3 , wherein each of the non-volatile memory cells are configured to operate in a linear region.
9. An analog neuromorphic memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each column is connected to a bit line and each memory cell comprises a word line terminal and a source line terminal;
a word line decoder circuit coupled to the word line terminals of the non-volatile memory cells through word lines, wherein the word lines are parallel to the bit lines, and wherein the word line decoder circuit is capable of applying a low voltage or a high voltage to coupled word line terminals; and
a sample and hold capacitor coupled to each word line.
10. The system of claim 9 , wherein a negative bias is applied to the word lines of each unselected memory cell during a program-and-verify operation or a read operation.
11. The system of claim 9 , wherein the capacitor in the sample and hold capacitor is provided by an inherent capacitance of a word line.
12. The system of claim 9 , wherein each of the non-volatile memory cells is a split-gate flash memory cell.
13. The system of claim 9 , wherein each of the non-volatile memory cells is a stacked-gate flash memory cell.
14. The system of claim 9 , wherein each of the non-volatile memory cells are configured to operate in a sub-threshold region.
15. The system of claim 9 , wherein each of the non-volatile memory cells are configured to operate in a linear region.
16. The system of claim 9 , wherein a S/H capacitor serves a voltage source for the wordline.
17. An analog neuromorphic memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each column is connected to a bit line and each memory cell comprises a word line terminal, a control gate terminal, and a source line terminal;
a control gate decoder circuit coupled to the control gate line terminals of the non-volatile memory cells through control gate lines, wherein the control gate lines are parallel to the bit lines, and wherein the control gate decoder circuit is capable of applying a low voltage or a high voltage to coupled control gate terminals; and
a sample and hold capacitor coupled to each word line.
18. The system of claim 17 , wherein a negative bias is applied to the word lines of each unselected memory cell during a program-and-verify operation or a read operation.
19. The system of claim 17 , wherein the sample and hold capacitor comprises control gate capacitance.
20. The system of claim 17 , wherein each of the non-volatile memory cells is a split-gate flash memory cell.
21. The system of claim 17 , wherein each of the non-volatile memory cells is a stacked-gate flash memory cell.
22. The system of claim 17 , wherein each of the non-volatile memory cells are configured to operate in a sub-threshold region.
23. The system of claim 17 , wherein each of the non-volatile memory cells are configured to operate in a linear region.
24. The system of claim 17 , wherein the S/H capacitor serves a voltage source for the control gate lines.
25. A current-to-voltage circuit comprising:
a reference circuit for receiving an input current and outputting a first voltage in response to the input current, the reference circuit comprising an input current source, an NMOS transistor, a cascoding bias transistor, and a reference memory cell;
a sample and hold circuit for receiving the first voltage and outputting a second voltage, the second voltage constituting a sampled value of the first voltage, the sample and hold circuit comprising a switch and capacitor.
26. The current to-voltage circuit of claim 25 , further comprising an amplifier for receiving the second voltage and outputting a third voltage.
27. The current-to-voltage circuit of claim 25 , wherein the second voltage is provided to a word line in a flash memory system.
28. The current-to-voltage circuit of claim 26 , wherein the second voltage is provided to a word line in a flash memory system.
29. The current-to-voltage circuit of claim 25 , wherein the second voltage is provided to a control gate line in a flash memory system.
30. The current-to-voltage circuit of claim 26 , wherein the second voltage is provided to a control gate line in a flash memory system.
31. A current-to-voltage circuit comprising:
a reference circuit for receiving an input current and outputting a first voltage in response to the input current, the reference circuit comprising an input current source, an NMOS transistor, a cascoding bias transistor, and a reference memory cell;
an amplifier for receiving the first voltage and outputting a second voltage;
a sample and hold circuit for receiving the second voltage and outputting a third voltage, the third voltage constituting a sampled value of the second voltage, the sample and hold circuit.
32. The current-to-voltage circuit of claim 31 , wherein the third voltage is provided to a word line in a flash memory system.
33. The current-to-voltage circuit of claim 31 , wherein the third voltage is provided to a control gate line in a flash memory system.
34. An analog neuromorphic memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns; and
a redundancy sector.
35. The system of claim 34 , further comprising a non-volatile register for storing system information.
36. An analog neuromorphic memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns; and
a non-volatile register for storing system information.