Hard and soft bit data from single read

1. An apparatus comprising:

a plurality of memory cells configured to be programmed to one of a plurality of data states, the plurality of data states comprising one or more error-prone data states;

sense circuitry configured to:

sense the memory cells at a plurality of read levels; and

determine a bit encoding for the memory cells; and

a communication circuit configured to communicate, in response to a single read command:

the bit encoding for the memory cells; and

an identification of a subset of the memory cells that are sensed as being in the one or more error-prone data states.

2. The apparatus of claim 1 , wherein the communication circuit is configured to communicate the bit encoding and the identification of the subset of the memory cells in a single communication message.

3. The apparatus of claim 1 , wherein the communication circuit:

communicates the identification of the subset of the memory cells in an intermediate data transfer; and

communicates the bit encoding in a final data transfer.

4. The apparatus of claim 1 , wherein the communication circuit communicates the identification of the subset of the memory cells before communicating the bit encoding for the plurality of memory cells.

5. The apparatus of claim 1 , wherein the one or more error-prone data states comprises a plurality of adjacent data states having a common bit encoding for at least one page.

6. The apparatus of claim 1 , wherein:

the plurality of read levels are positioned at symbol boundaries; and

the sense circuitry is further configured to sense the plurality of memory cells at an additional read level in response to the read command.

7. An apparatus comprising:

a plurality of multi-level memory cells;

a communication interface configured to couple the apparatus to a memory controller; and

sense circuitry configured to execute a single page read operation by:

performing a first sense operation to sense the memory cells at a first read level;

performing a second sense operation to sense the memory cells using a second read level;

transmitting reliability data over the communication interface based on either the first sense operation or based on both the first sense operation and the second sense operation; and

transmitting hard bit data indicating data stored in the plurality of memory cells over the communication interface, wherein the hard bit data is based on the first sense operation and the second sense operation.

8. The apparatus of claim 7 , further comprising a first set of data latches and a second set of data latches, wherein the sense circuitry is further configured to:

store first values based on the first sense operation in the first set of data latches;

store second values based on the second sense operation in the second set of data latches;

execute a logical operation on the first values and the second values to generate additional values; and

store the additional values in the first set of data latches, thereby overwriting the first values.

9. The apparatus of claim 8 , wherein the reliability data comprises the first values.

10. The apparatus of claim 8 , wherein the reliability data comprises the additional values.

11. The apparatus of claim 7 , wherein:

the memory cells are programmed to a first plurality of programming groups associated with a first bit value and a second plurality of programming groups associated with a second bit value; and

the reliability data indicate a subset of the memory cells that are programmed to one programming group of the first plurality of programming groups.

12. The apparatus of claim 7 , wherein:

the first read level distinguishes an erase programming state from non-erase programming states.

13. The apparatus of claim 7 , wherein the sense circuitry is configured to transmit the reliability data using an intermediate transfer.

14. A system comprising:

a communication bus;

a memory controller; and

a non-volatile memory die electrically coupled to the memory controller via the communication bus, the non-volatile memory die comprising:

a plurality of memory cells; and

control circuitry configured to, in response to a single read command received from the memory controller:

sense the plurality of memory cells using a first read level;

sense the plurality of memory cells using a second read level;

at a first time, transmit soft bit data based at least on the first read level to the memory controller; and

at a second time after the first time, transmit hard bit data based on the first read level and the second read level to the memory controller.

15. The system of claim 14 , wherein the memory controller comprises a decoder configured to:

receive the soft bit data and the hard bit data based on the first read level and the second read level; and

decode the plurality of memory cells based on the soft bit data and the hard bit data based on the first read level and the second read level.

16. The system of claim 15 , wherein:

the decoder is configured to generate reliability values based on the soft bit data; and

said decoding the plurality of memory cells is based at least in part on the reliability values.

17. The system of claim 16 , wherein the reliability values are log-likelihood ratio values.

18. The system of claim 14 , wherein the control circuitry is further configured to, at a third time between the first time and the second time, transmit additional soft bit data to the memory controller.

19. The system of claim 14 , wherein the control circuitry is further configured to:

perform an additional sense at an additional read level; and

transmit data based on the additional sense to the memory controller.