Systems and methods for implementing a scalable system
Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
1. A multi-chip system comprising:
a first chip;
an interfacing bar coupled with the first chip; and
a second chip coupled with the interfacing bar along a longitudinal length of the interfacing bar; and
a third chip coupled with the interfacing bar along the longitudinal length of the interfacing bar, wherein the second chip is coupled with the interfacing bar along the longitudinal length of the interfacing bar further away from the first chip than the third chip.
2. The multi-chip system of claim 1 , the interfacing bar comprises a routing layer extending a substantial portion of a longitudinal length of the interfacing bar.
3. The multi-chip system of claim 2 , wherein:
the routing layer of the interfacing bar comprises a plurality of metal layers including a lower wiring layer and an upper wiring layer characterized by wider wiring than the lower wiring layer; and
the second chip is electrically coupled with the first chip through a first wire running a substantial distance of the longitudinal length in upper wiring layer, and the third chip electrically is coupled with the first chip through a second wire in the lower wiring layer, wherein the first wire is wider than the second wire.
4. The multi-chip system of claim 2 , wherein the interfacing bar comprises a discrete head component and one or more discrete active components, wherein the discrete head component and the one or more discrete active components are electrically coupled with the routing layer.
5. The multi-chip system of claim 4 , wherein the discrete head component and the one or more discrete active components are in an insulating layer.
6. The multi-chip system of claim 2 , further comprising a second interfacing bar, a plurality of additional chips coupled with the second interfacing bar, and a bridge that couples the interfacing bar to the second interfacing bar.
7. The multi-chip system of claim 2 , wherein the interfacing bar comprises a head section and an extension section extending along the longitudinal length of the interfacing bar, wherein the head section is wider than the extension section.
8. The multi-chip system of claim 1 , wherein the interfacing bar comprises a deserializer, a serializer, and a plurality of repeaters between the deserializer and the serializer.
9. The multi-chip system of claim 1 , wherein the interfacing bar is an optical interconnect bar.
10. The multi-chip system of claim 9 , wherein the optical interconnect bar includes an electrical-to-optical converter component and an optical-to-electrical converter component.
11. The multi-chip system of claim 1 , further comprising:
a substrate including a routing layer, and a high density bridge within the routing layer;
wherein the first chip is mounted on the routing layer, the interfacing bar is mounted on the routing layer, and the first chip and the interfacing bar are electrically coupled with the high density bridge within the routing layer.
12. The multi-chip system of claim 11 , wherein the high density bridge includes an active device.
13. The multi-chip system of claim 11 , wherein an additional plurality of chips are mounted on the routing layer, and electrically coupled with the interfacing bar with routing in the routing layer.
14. The multi-chip system of claim 11 , wherein the substrate is characterized by a composite coefficient of thermal expansion (CTE) that is matched within +/−4 ppm/C of an effective CTE of a composite topology including the first chip, the interfacing bar, and the second chip.
15. The multi-chip system of claim 14 , wherein the substrate is coupled with a board with a flex circuit.
16. The multi-chip system of claim 1 , further comprising:
a substrate including a routing layer;
wherein the first chip is mounted on the routing layer, the interfacing bar is mounted on the routing layer, and the first chip and the interfacing bar are electrically coupled by the routing layer.
17. The multi-chip system of claim 16 , wherein the second chip, the third chip and an additional plurality of chips are mounted on the routing layer and electrically coupled with the interfacing bar by the routing layer.
18. The multi-chip system of claim 17 , wherein the substrate is characterized by a composite coefficient of thermal expansion (CTE) that is matched within +/−4 ppm/C of an effective CTE of a composite topology on the substrate including the first chip, the interfacing bar, and the second chip.
19. The multi-chip system of claim 18 , wherein the substrate is coupled with a board with a flex circuit.
20. The multi-chip system of claim 1 , further comprising:
a lower redistribution layer (RDL);
a first molding layer on the lower RDL, wherein the interfacing bar is encapsulated in the first molding layer;
a second molding layer on the first molding layer, wherein the first chip is encapsulated in the second molding layer; and
wherein the second chip, the second chip and an additional plurality of chips are mounted on top of the second molding layer.
21. The multi-chip system of claim 1 , further comprising a first molding layer, wherein the interfacing bar is encapsulated in the first molding layer, the first chip is mounted on top of the first molding layer, and the second chip, and an additional plurality of chips are mounted on top of the second molding layer.