Three-dimensional memory device containing channels with laterally pegged dielectric cores
A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.
1. A three-dimensional memory device, comprising:
a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers located over a substrate;
an inter-tier insulating assembly located over the first-tier alternating stack and including a plurality of dielectric strips, wherein each of the plurality of dielectric strips includes dielectric peg portions that laterally protrude from a dielectric rail portion;
a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers located over the inter-tier insulating assembly;
memory openings vertically extending through the first-tier alternating stack, the inter-tier insulating assembly, and the second-tier alternating stack, wherein each of the memory openings comprises a side aperture through which a respective one of the dielectric peg portions extend inward; and
memory opening fill structures located in a respective one of the memory openings and comprising a memory film, a semiconductor channel, and a dielectric core comprising a dielectric fill material and adjoined to the respective one of the dielectric peg portions.
2. The three-dimensional memory device of claim 1 , wherein each of the semiconductor channels has a respective annular horizontal cross-sectional shape at levels of the first-tier alternating stack and at levels of the second-tier alternating stack, and has a respective shape of a block arc at a level of the inter-tier insulating assembly.
3. The three-dimensional memory device of claim 2 , wherein each of the memory films has a respective annular horizontal cross-sectional shape at the levels of the first-tier alternating stack and at the levels of the second-tier alternating stack, and has a respective shape of a block arc at the level of the inter-tier insulating assembly.
4. The three-dimensional memory device of claim 1 , wherein each interface between the dielectric cores and the dielectric peg portions comprises a convex vertical surface of a respective one of the dielectric cores and a concave vertical surface of a respective one of the dielectric peg portions.
5. The three-dimensional memory device of claim 1 , wherein the inter-tier insulating assembly comprises insulating material strips that are interlaced with the plurality of dielectric strips, wherein a laterally alternating sequence of insulating material strips and dielectric strips that alternate along a first horizontal direction is present between the first-tier alternating stack and the second-tier alternating stack.
6. The three-dimensional memory device of claim 5 , wherein each of the plurality of insulating material strips contacts two columns of memory opening fill structures that extend along a second horizontal direction that is perpendicular to the first horizontal direction.
7. The three-dimensional memory device of claim 5 , further comprising:
a backside trench vertically extending through the first-tier alternating stack, the inter-tier insulating assembly, and the second-tier alternating stack, laterally extending along the first horizontal direction, and having a uniform width along a second horizontal direction that is perpendicular to the first horizontal direction; and
a backside trench fill structure located in the backside trench, wherein each strip within the laterally alternating sequence of insulating material strips and dielectric strips contacts a sidewall of the backside trench fill structure.
8. The three-dimensional memory device of claim 5 , wherein each of the plurality of dielectric strips has two sets of straight sidewall segments, wherein each set of straight sidewall segments includes a plurality of straight sidewall segments located within a respective vertical plane that is perpendicular to the first horizontal direction.
9. The three-dimensional memory device of claim 1 , further comprising:
a single crystalline semiconductor material layer located in or over the substrate, wherein the semiconductor channel comprises an epitaxial semiconductor channel that is epitaxially aligned to the single crystalline semiconductor material layer; and
drain regions comprising a doped epitaxial semiconductor material contacting an upper end of, and epitaxially aligned to, a respective one of the epitaxial semiconductor channels and contacting a top surface of a respective one of the dielectric cores.
10. The three-dimensional memory device of claim 9 , further comprising a source contact layer comprising a doped single crystalline semiconductor material and contacting, and epitaxially aligned to, the single crystalline semiconductor material layer and the epitaxial semiconductor channels.
11. The three-dimensional memory device of claim 10 , wherein the source contact layer contacts and laterally surrounds each of the dielectric cores.
12. The three-dimensional memory device of claim 10 , wherein each interface between the a source contact layer and the epitaxial semiconductor channels comprises an annular convex tapered surface of the source contact layer and an annular concave tapered surface of a respective one of the epitaxial semiconductor channels.
13. The three-dimensional memory device of claim 1 , wherein:
the epitaxial semiconductor channels comprise a material selected from single crystalline silicon, a single crystalline silicon-germanium alloy, or a single crystalline III-V compound semiconductor material; and
the plurality of dielectric strips comprises a material selected from undoped silicate glass, a doped silicate glass, or organosilicate glass.