High-density low voltage non-volatile differential memory bit-cell with shared plate-line
Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).
1. A differential bit-cell comprising:
a first transistor having a gate terminal coupled to a word-line (WL) and one of a source or drain terminal coupled to a first bit-line (BL);
a second transistor having a gate terminal coupled to the WL and one of a source or drain terminal coupled to a second bit-line (BLB), wherein the BLB is to provide a signal which is inverse of a signal on BL;
a first non-volatile structure coupled to one of the drain or source of the first transistor, and further coupled to a plate-line (PL); and
a second non-volatile structure coupled to one of the drain or source of the second transistor, and further coupled to the PL;
wherein each of the first and second non-volatile structures comprises:
a first layer comprising a first refractive inter-metallic material, wherein the first layer is adjacent to the drain or source of the first or second transistor;
a second layer comprising a first conductive oxide, wherein the second layer is adjacent to the first layer;
a third layer comprising a perovskite material, wherein the third layer is adjacent to the second layer;
a fourth layer comprising a second conductive oxide, wherein the fourth layer is adjacent to the third layer;
a fifth layer comprising a second refractive inter-metallic material, wherein the fifth layer is adjacent to the PL and adjacent to the fourth layer;
a sixth layer directly adjacent to first sides of the first, second, third, fourth and fifth layers; and
a seventh layer directly adjacent to second sides of the first, second, third, fourth and fifth layers, wherein the sixth and the seventh layers comprise a barrier material.
2. The differential bit-cell of claim 1 , wherein the first and second transistors are of a same conductivity type.
3. The differential bit-cell of claim 1 , wherein the first and second transistors are one of planar transistors or non-planar transistors.
4. The differential bit-cell of claim 1 , wherein:
the barrier material includes one or more of an oxide of: Ti, Al, or Mg;
the perovskite material is doped with La or Lanthanides; or
the refractive inter-metallic material includes one or more of: Ti, Al, Ta, W, or Co.
5. The differential bit-cell of claim 1 , wherein the first and second transistors are positioned in a backend of a die, or wherein the first and second transistors are positioned in a frontend of the die.
6. The differential bit-cell of claim 1 , wherein the first or second conductive oxides include oxides of one or more of: Ir, Ru, Pd, Ps, or Re.
7. The differential bit-cell of claim 1 , wherein the perovskite material includes one of: LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.
8. The differential bit-cell of claim 1 , wherein the perovskite material includes one of: La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.
9. The differential bit-cell of claim 1 , wherein the first non-volatile structure is cylindrical in shape.
10. The differential bit-cell of claim 1 , wherein the perovskite material is doped with Sc or Mn to control leakage through the third layer.
11. The differential bit-cell of claim 1 , wherein the first transistor and first non-volatile structure are controlled to store data of a first value, wherein the second transistor and second non-volatile structure are controlled to store data of a second value, and wherein the first value is an inverse of the second value.
12. A system comprising:
an artificial intelligence processor; and
a non-volatile memory coupled to the artificial intelligence processor, wherein the non-volatile memory includes differential bit-cells, wherein one of the differential bit-cell includes:
a first transistor having a gate terminal coupled to a word-line (WL) and one of a source or drain terminal coupled to a first bit-line (BL);
a second transistor having a gate terminal coupled to the WL and one of a source or drain terminal coupled to a second bit-line (BLB), wherein the BLB is to provide a signal which is inverse of a signal on BL;
a first non-volatile structure coupled to one of the drain or source of the first transistor, and further coupled to a plate-line (PL); and
a second non-volatile structure coupled to one of the drain or source of the second transistor, and further coupled to the PL;
wherein each of the first and second non-volatile structures comprises:
a first layer comprising a first refractive inter-metallic material, wherein the first layer is adjacent to the drain or source of the first or second transistor;
a second layer comprising a first conductive oxide, wherein the second layer is adjacent to the first layer;
a third layer comprising a perovskite material, wherein the third layer is adjacent to the second layer;
a fourth layer comprising a second conductive oxide, wherein the fourth layer is adjacent to the third layer;
a fifth layer comprising a second refractive inter-metallic material, wherein the fifth layer is adjacent to the PL and adjacent to the fourth layer;
a sixth layer directly adjacent to first sides of the first, second, third, fourth and fifth layers; and
a seventh layer directly adjacent to second sides of the first, second, third, fourth and fifth layers, wherein the sixth and the seventh layers comprise a barrier material.
13. The system of claim 12 , wherein the first and second transistors are of a same conductivity type, and wherein the first and second transistors are one of planar transistors or non-planar transistors.
14. The system of claim 12 , wherein:
the barrier material includes one or more of an oxide of: Ti, Al, or Mg;
the perovskite material is doped with La or Lanthanides;
the refractive inter-metallic material includes one or more of: Ti, Al, Ta, W, or Co; and
the first or second conductive oxides include oxides of one or more of: Ir, Ru, Pd, Ps, or Re.
15. The system of claim 12 , wherein the first and second transistors are positioned in a backend of a die, or wherein the first and second transistors are positioned in a frontend of the die.
16. The system of claim 12 , wherein the perovskite material includes one of: LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.
17. The system of claim 12 , wherein the perovskite material includes one of: La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.
18. A method for forming a differential bit-cell, the method comprising:
fabricating a first transistor having a gate terminal coupled to a word-line (WL) and one of a source or drain terminal coupled to a first bit-line (BL);
fabricating a second transistor having a gate terminal coupled to the WL and one of a source or drain terminal coupled to a second bit-line (BLB), wherein the BLB is to provide a signal which is inverse of a signal on BL;
forming a first ferroelectric structure coupled to one of the drain or source of the first transistor, and further coupled to a plate-line (PL); and
forming a second ferroelectric structure coupled to one of the drain or source of the second transistor, and further coupled to the PL, wherein the first and second ferroelectric structures comprise a perovskite material;
wherein forming the first or second ferroelectric structures comprises:
forming a first layer comprising a first refractive inter-metallic material, wherein the first layer is adjacent to the drain or source of the first or second transistor;
forming a second layer comprising a first conductive oxide, wherein the second layer is adjacent to the first layer;
forming a third layer comprising a perovskite material, wherein the third layer is adjacent to the second layer;
forming a fourth layer comprising a second conductive oxide, wherein the fourth layer is adjacent to the third layer;
forming a fifth layer comprising a second refractive inter-metallic material, wherein the fifth layer is adjacent to the PL and adjacent to the fourth layer;
forming a sixth layer adjacent to a first side of the first, second, third, fourth and fifth layers;
forming a sixth layer directly adjacent to first sides of the first, second, third, fourth and fifth layers; and
forming a seventh layer directly adjacent to second sides of the first, second, third, fourth and fifth layers, wherein the sixth and the seventh layers comprise a barrier material.
19. The method of claim 18 , wherein:
the barrier material includes one or more of an oxide of: Ti, Al, or Mg;
the first and/or second transistor is one of a planar or non-planar transistor;
the perovskite material is doped with La or Lanthanides;
the refractive inter-metallic material includes one or more of: Ti, Al, Ta, W, or Co; and
the first or second conductive oxides include oxides of one or more of: Ir, Ru, Pd, Ps, or Re.
20. The method of claim 18 comprising positioning the first and second transistors in a backend of a die.
21. The method of claim 18 comprising positioning the first and second transistors in a frontend of a die.
22. The method of claim 18 , wherein the perovskite material includes one of: LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.
23. The method of claim 18 , wherein the perovskite material includes one of: La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.
24. The method of claim 18 , wherein the first and second transistors are of a same conductivity type.