Apparatus and method to improve sensing noise margin in a non-linear polar material based bit-cell
Described herein is a memory sensing scheme that improves noise margin. In at least one embodiment, one or more circuitries are described that are coupled to a bit-cell, wherein the bit-cell is coupled to a plate-line and a bit-line, wherein the one or more circuitries are to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on a plate-line and a second floating charge on a bit-line.
1. An apparatus comprising:
a bit-cell coupled to a plate-line, a word-line, and a bit-line, wherein the plate-line is parallel to the bit-line, and wherein the word-line controls a transistor of the bit-cell; and
a sense circuitry coupled to the plate-line and the bit-line, wherein the sense circuitry is to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on the plate-line, and a second floating charge on the bit-line, wherein the bit-cell comprises two or more capacitors, wherein a first capacitor of the two or more capacitors has a first terminal coupled to the plate-line and a second terminal coupled to the transistor, wherein a gate of the transistor is coupled to the word-line, and wherein a source or drain terminal of the transistor is coupled to the bit-line.
2. The apparatus of claim 1 comprising a first switch to pre-charge or pre-discharge the plate-line to a first reference voltage before the sense circuitry is to sense the first floating charge on the plate-line.
3. The apparatus of claim 1 comprising a second switch to pre-charge or pre-discharge the bit-line to a second reference voltage before the sense circuitry is to sense the second floating charge on the bit-line.
4. The apparatus of claim 1 , wherein the sense circuitry is to detect a difference between the first floating charge and the second floating charge.
5. The apparatus of claim 1 , wherein the bit-cell comprises a capacitor having a first terminal coupled to the plate-line and a second terminal coupled to the transistor, wherein a gate of the transistor is coupled to the word-line, and wherein a source or drain terminal of the transistor is coupled to the bit-line.
6. The apparatus of claim 5 , wherein the capacitor comprises a non-linear polar material.
7. The apparatus of claim 6 , wherein the non-linear polar material is one of a ferroelectric, a paraelectric, or a non-linear dielectric material.
8. The apparatus of claim 6 , wherein the non-linear polar material is doped with one or more elements of a 3d, 4d, 5d, 6d, 4f, or 5f series of a periodic table.
9. The apparatus of claim 6 , wherein the non-linear polar material includes one of:
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
bismuth ferrite (BFO);
barium titanate (BTO);
BFO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
BTO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
LBFO doped with Mn;
lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La, Nb, Mn, or 5d series elements;
bismuth ferrite (BFO) with a doping material, wherein the doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of a 3d, 4d, 5d, 6d, 4f or 5f series of the periodic table;
a relaxor ferroelectric material which includes one of; lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides as Hf (1-x) E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y; Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, E y doped HfO 2 , where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ or ‘y’ is a fraction; or niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100, or a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectric; or
a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, or a PMN-PT based relaxor ferroelectric.
10. The apparatus of claim 1 , wherein the two or more capacitors are planar capacitors that are arranged in a stacked and/or folded configuration.
11. The apparatus of claim 1 , wherein the transistor is a first transistor, wherein the first transistor is coupled to a storage node, wherein the bit-cell comprises:
a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal coupled to a sense line, and a second drain terminal coupled to a bias; and
a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of a first capacitor of the plurality of capacitors is coupled to the plate-line, wherein the plurality of capacitors are planar capacitors that are arranged in a stacked and/or folded configuration.
12. An apparatus comprising:
one or more circuitries coupled to a bit-cell, wherein the bit-cell is coupled to a plate-line and a bit-line, wherein the one or more circuitries are to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on the plate-line and a second floating charge on the bit-line, wherein the bit-cell comprises two or more capacitors, wherein a first capacitor of the two or more capacitors has a first terminal coupled to the plate-line and a second terminal coupled to the transistor, wherein a gate of the transistor is coupled to the word-line, and wherein a source or drain terminal of the transistor is coupled to the bit-line.
13. The apparatus of claim 12 comprising: a first switch to pre-charge or pre-discharge the plate-line to a first reference voltage before the one or more circuitries are to sense the first floating charge on the plate-line.
14. The apparatus of claim 13 comprising: a second switch to pre-charge or pre-discharge the bit-line to a second reference voltage before the one or more circuitries are to sense the second floating charge on the bit-line.
15. The apparatus of claim 14 , wherein the first reference voltage is substantially higher than the second reference voltage, or the second reference voltage is substantially higher than the first reference voltage.
16. The apparatus of claim 12 , wherein the one or more circuitries are to detect a difference between the first floating charge and the second floating charge.
17. A system comprising:
a memory to store instructions;
a processor circuitry to execute the instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
a bit-cell coupled to a plate-line, a word-line, and a bit-line, wherein the plate-line is parallel to the bit-line, and wherein the word-line controls a transistor of the bit-cell; and
a sense circuitry coupled to the plate-line and the bit-line, wherein the sense circuitry is to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on the plate-line and a second floating charge on the bit-line, wherein the bit-cell comprises two or more capacitors, wherein a first capacitor of the two or more capacitors has a first terminal coupled to the plate-line and a second terminal coupled to the transistor, wherein a gate of the transistor is coupled to the word-line, and wherein a source or drain terminal of the transistor is coupled to the bit-line.
18. The system of claim 17 , wherein the memory comprises:
a first switch to pre-charge or pre-discharge the plate-line to a first reference voltage before the sense circuitry is to sense the first floating charge on the plate-line; and
a second switch to pre-charge or pre-discharge the bit-line to a second reference voltage before the sense circuitry is to sense the second floating charge on the bit-line.
19. The system of claim 18 , wherein the sense circuitry is to detect a difference between the first floating charge and the second floating charge.