Non-linear polar material based multi-capacitor bit-cell with shared gain element with series transistor
Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.
1 . An apparatus comprising:
a first plurality of capacitors, wherein a first individual capacitor of the first plurality of capacitors is coupled to a first node and a first individual plate-line;
a second plurality of capacitors, wherein a second individual capacitor of the second plurality of capacitors is coupled to a second node and a second individual plate-line;
a first transistor having a first gate terminal coupled to a first control, wherein the first transistor is coupled to the first node;
a second transistor having a second gate terminal coupled to by a second control, wherein the second transistor is coupled to the second node;
a third node, wherein the first transistor and the second transistor are coupled to the third node;
a third transistor having a third gate terminal coupled to the third node;
a fourth transistor coupled in series with the third transistor, wherein the fourth transistor is coupled to a sense-line; and
a fifth transistor coupled to the third node and a bit-line.
2 . The apparatus of claim 1 , wherein the third transistor has a third drain terminal coupled to a reference.
3 . The apparatus of claim 1 , wherein the fourth transistor is controllable to reduce leakage through the third node.
4 . The apparatus of claim 1 , wherein the fifth transistor is controllable by a word-line, and wherein the fourth transistor is smaller in size than the third transistor.
5 . The apparatus of claim 1 , wherein the fourth transistor is controllable by a word-line.
6 . The apparatus of claim 1 , wherein the fourth transistor is controllable by a read word-line.
7 . The apparatus of claim 1 , wherein the first individual capacitor comprises a non-linear polar material.
8 . The apparatus of claim 7 , wherein the non-linear polar material is directly on the first node.
9 . The apparatus of claim 7 , wherein the non-linear polar material is one of a ferroelectric material, a paraelectric material, or a non-linear dielectric material.
10 . The apparatus of claim 7 , wherein the non-linear polar material is doped with one or more elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of a periodic table.
11 . The apparatus of claim 7 , wherein the non-linear polar material includes one of:
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
bismuth ferrite (BFO);
barium titanate (BTO);
BFO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
BTO doped with one of: Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, or Zn;
LBFO doped with Mn;
lead zirconium titanate (PZT) or PZT with a first doping material, wherein the first doping material is one of La, Nb, Mn, or 5d series elements;
bismuth ferrite (BFO) with a second doping material, wherein the second doping material is one of lanthanum, elements from lanthanide series of a periodic table, or elements of a 3d, 4d, 5d, 6d, 4f, and 5f series of the periodic table;
a relaxor ferroelectric material which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a hexagonal ferroelectric which includes one of: YMnO 3 or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , wherein R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides as Hf (1-x) E x O y , where E includes one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, where x and y are first and second fractions, respectively;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, where x and y are third and fourth fractions, respectively;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; or
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxyfluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, wherein ‘n’ is between 1 and 100, or a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectric; or
a paraelectric material that comprises SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, or a PMN-PT based relaxor ferroelectric.
12 . The apparatus of claim 1 , wherein the first plurality of capacitors and the second plurality of capacitors are planar capacitors that are arranged in a stacked and/or folded configuration.
13 . The apparatus of claim 12 , wherein the first individual capacitor comprises a non-linear polar material.
14 . An apparatus comprising:
a first plurality of capacitors, wherein a first individual capacitor of the first plurality of capacitors is coupled to a first node and a first individual plate-line;
a second plurality of capacitors, wherein a second individual capacitor of the second plurality of capacitors is coupled to a second node and a second individual plate-line;
a first transistor having a first gate terminal coupled to a first control, wherein the first transistor is coupled to the first node;
a second transistor having a second gate terminal coupled to by a second control, wherein the second transistor is coupled to the second node;
a third node, wherein the first transistor and the second transistor are coupled to the third node;
a third transistor having a third gate terminal coupled to the third node and to a sense-line;
a fourth transistor coupled in series with the third transistor, wherein the fourth transistor is coupled to a reference; and
a fifth transistor coupled to the third node and a bit-line.
15 . The apparatus of claim 14 , wherein the fifth transistor is controllable by a word-line, wherein the first individual plate-line is parallel to the word-line.
16 . The apparatus of claim 15 , wherein the fourth transistor has a fourth gate terminal controllable by the word-line.
17 . The apparatus of claim 15 , wherein the fourth transistor has a fourth gate terminal controllable by a read word-line.
18 . The apparatus of claim 14 , wherein the fourth transistor is controllable to reduce leakage through the third node to the sense-line.
19 . The apparatus of claim 14 , wherein the fourth transistor is smaller in size than the third transistor.
20 . A system comprising:
a memory to store instructions;
a processor circuitry to execute the instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
a first plurality of capacitors, wherein a first individual capacitor of the first plurality of capacitors is coupled to a first node and a first individual plate-line;
a second plurality of capacitors, wherein a second individual capacitor of the second plurality of capacitors is coupled to a second node and a second individual plate-line;
a first transistor having a first gate terminal coupled to a first control, wherein the first transistor is coupled to the first node;
a second transistor having a second gate terminal coupled to by a second control, wherein the second transistor is coupled to the second node;
a third node, wherein the first transistor and the second transistor are coupled to the third node;
a third transistor having a third gate terminal coupled to the third node;
a fourth transistor coupled in series with the third transistor, wherein the fourth transistor is coupled to a sense-line; and
a fifth transistor coupled to the third node and a bit-line.