Interconnect structures and methods of forming the same
Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
1. A method comprising:
etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a first layer of a first conductive material;
treating the via opening with a plasma to physically remove etching residue from sidewalls and a bottom of the via opening;
soaking the conductive feature with a halide of the first conductive material, residual halide of the first conductive material remaining in the via opening after the soaking;
reducing the residual halide of the first conductive material to form a second layer of the first conductive material on the first layer;
depositing a conductive via in the via opening on the second layer of the first conductive material; and
forming a conductive line in the trench on one or more exposed dielectric surfaces of the trench and on the conductive via.
2. The method of claim 1 , wherein the first conductive material is tungsten, and the halide of the first conductive material is tungsten hexafluoride.
3. The method of claim 1 , wherein reducing the residual halide of the first conductive material comprises exposing the residual halide to hydrogen.
4. The method of claim 1 , wherein forming the conductive line comprises conformally depositing a material of the conductive line in the trench on the one or more exposed dielectric surfaces.
5. The method of claim 4 , wherein depositing the material of the conductive line does not include depositing a seed layer for depositing the material of the conductive line.
6. The method of claim 4 , wherein no metal-containing barrier layer is deposited in the interconnect opening before depositing the material of the conductive line.
7. The method of claim 4 , further comprising:
performing a nucleation enhancement treatment on the one or more exposed dielectric surfaces of the trench before depositing the material of the conductive line.
8. The method of claim 7 , wherein the nucleation enhancement treatment increases a number of nucleation sites on surfaces of the dielectric layers exposed in the trench by breaking chemical bonds of the surfaces of the dielectric layers exposed in the trench.
9. A method comprising:
etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a conductive material, wherein etching the interconnect opening forms an etching residue in the via opening and forms a native oxide on a surface of the conductive feature;
cleaning the via opening comprising:
removing the etching residue by treating the via opening with a plasma; and
removing the native oxide by exposing the surface of the conductive feature to a halide of the conductive material;
depositing a conductive via in the cleaned via opening;
performing a nucleation enhancement treatment on one or more exposed dielectric surfaces of the trench; and
forming a conductive line in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.
10. The method of claim 9 , wherein treating the via opening with the plasma comprises:
bombarding the via opening with hydrogen for a duration of from about 5 seconds to about 300 seconds.
11. The method of claim 9 , wherein exposing the surface of the conductive feature comprises:
soaking the surface of the conductive feature with the halide of the conductive material, residual halide remaining in the via opening after the soaking.
12. The method of claim 9 , wherein cleaning the via opening further comprises:
redepositing additional conductive material on the conductive feature by exposing the surface of the conductive feature to a reducing agent.
13. The method of claim 12 , wherein exposing the surface of the conductive feature to the reducing agent comprises:
reducing residual halide with hydrogen, the reduced residual halide forming the additional conductive material.
14. The method of claim 9 further comprising:
depositing the conductive feature over the semiconductor substrate with a plurality of precursors for the conductive material, the halide of the conductive material being one of the precursors for the conductive material.
15. The method of claim 9 , wherein the nucleation enhancement treatment increases a number of nucleation sites on the exposed dielectric surfaces of the trench by breaking chemical bonds of the exposed dielectric surfaces of the trench.
16. The method of claim 15 , wherein forming the conductive line comprises conformally depositing a material of the conductive line in the trench on the exposed dielectric surfaces of the trench without depositing a seed layer for the material of the conductive line.
17. The method of claim 9 , wherein the nucleation enhancement treatment increases a number of nucleation sites on the one or more exposed dielectric surfaces of the trench, and wherein forming the conductive line comprises:
adsorbing a conductive fill material of the conductive line into the nucleation sites; and
planarizing the conductive fill material of the conductive line and an upper dielectric layer of the one or more dielectric layers, wherein a top surface of the upper dielectric layer and a lowest point of a top surface of the conductive fill material are coplanar after the planarizing.
18. The method of claim 9 , wherein the conductive material is tungsten, and the halide of the conductive material is tungsten hexafluoride.
19. A method comprising:
depositing a conductive feature over a substrate, the depositing comprising providing a plurality of precursors for a first conductive material;
depositing one or more dielectric layers over the conductive feature;
etching an interconnect opening through the one or more dielectric layers, the interconnect opening having a via portion and a line portion over the via portion;
cleaning sidewalls and bottom surfaces of the interconnect opening with a halide of the first conductive material, the halide of the first conductive material being one of the precursors for the first conductive material;
depositing a conductive via in the via portion of the cleaned interconnect opening, the conductive via contacting the conductive feature; and
depositing a conductive line in the line portion of the cleaned interconnect opening.
20. The method of claim 19 further comprising:
after cleaning the interconnect opening, depositing a layer of the first conductive material on the conductive feature in the cleaned interconnect opening.