IP Library › Granted Patent US 12,300,540
Granted Patent B2
US 12,300,540 · App. 17/401,633 · Granted May 13, 2025

Conductive feature of semiconductor device and method of forming same

Inventors: Bo-Yu Lai (Taipei, TW); Chin-Szu Lee (Taoyuan, TW); Szu-Hua Wu (Zhubei, TW); Shuen-Shin Liang (Hsinchu, TW); Chia-Hung Chu (Taipei, TW); Keng-Chu Lin (Ping-Tung, TW); Sung-Li Wang (Zhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L21/76867H01L21/76847H01L21/76883H01L23/53266H01L29/401H01L29/66795H01L23/5226H01L29/41791H01L29/45H01L29/456
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Quick Facts
Patent No.
US 12,300,540
App. No.
17/401,633
Granted
May 13, 2025
Kind
B2
Abstract

A method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region includes a homogeneous mixture of the first conductive material and the second conductive material.

Claims (41)

1. A method comprising:

forming a device region over a substrate;

forming a first dielectric layer over the device region;

forming an opening in the first dielectric layer;

conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening;

depositing a second conductive material on the first conductive material to completely fill the opening, wherein the second conductive material is different from the first conductive material;

performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region comprises a homogeneous mixture of the first conductive material and the second conductive material;

performing a planarization process to remove excess first conductive material and excess second conductive material;

after performing the planarization process, depositing a capping layer over the second conductive material, wherein the capping layer comprises the second conductive material;

forming a first conductive feature covering the capping layer; and

after forming the first conductive feature, performing a second thermal process to diffuse the capping layer into the first conductive feature.

2. The method of claim 1 , wherein the first conductive material is Ru and the second conductive material is Co.

3. The method of claim 1 , wherein the first thermal process diffuses the first conductive material into the second conductive material.

4. The method of claim 1 , wherein the first thermal process comprises an anneal performed at a temperature in the range of 100° C. to 1000° C.

5. The method of claim 1 , wherein the opening in the first dielectric layer exposes a surface of a second conductive feature, and wherein the first thermal process diffuses the first conductive material into the second conductive feature.

6. A method comprising:

forming a first dielectric layer over a first conductive feature;

forming an opening in the first dielectric layer, wherein the opening exposes a surface of the first conductive feature;

depositing a liner layer along sidewalls of the opening and on the exposed surface of the first conductive feature, the liner layer comprising a first material;

depositing a filler layer on the liner layer, wherein the filler layer comprises a second material different from the first material, wherein an interface between the liner layer and the filler layer has a step concentration profile, wherein the filler layer fills the opening;

performing a first annealing process, wherein after performing the first annealing process, the interface between the liner layer and the filler layer comprises a homogenous mixture of the first material and the second material; and

forming a second conductive feature over the liner layer and the filler layer, wherein the second conductive feature extends on a top surface of the first dielectric layer, wherein the second conductive feature comprises a layer of the second material.

7. The method of claim 6 further comprising performing a second annealing process, wherein after performing the second annealing process, an interface between the second conductive feature and the liner layer comprises a homogenous mixture of the first material and the second material.

8. The method of claim 6 , wherein a width of the second conductive feature is greater than a width of the opening.

9. The method of claim 6 , wherein the second material is cobalt.

10. The method of claim 6 , wherein after performing the first annealing process, an interface between the liner layer and the first conductive feature comprises a homogenous mixture of the first material and the second material.

11. The method of claim 6 , wherein forming the second conductive feature comprises depositing a layer of the first material on the layer of the second material.

12. The method of claim 6 further comprising depositing a second dielectric layer over the first dielectric layer, wherein the opening extends through the second dielectric layer.

13. A method comprising:

forming an opening in an insulating layer;

depositing a first metal to form a first metal region, wherein the first metal region extends on a bottom surface of the opening and sidewalls of the opening, wherein top surfaces of the first metal region and the insulating layer are level;

depositing a second metal on the first metal region to form a second metal region, wherein the second metal is different than the first metal, wherein a top surface of the second metal region is higher than the top surface of the insulating layer;

depositing the first metal over the second metal region; and

performing an anneal process to form a third metal region over the second metal region, wherein the third metal region comprises a mixture of the first metal and the second metal.

14. The method of claim 13 , wherein after performing the anneal process, the top surface of the first metal region is lower than the top surface of the insulating layer.

15. The method of claim 13 , wherein the top surface of the insulating layer is free of the second metal region.

16. The method of claim 13 , wherein a width of the third metal region is greater than a width of the first metal region.

17. The method of claim 1 , wherein the second thermal process further diffuses the capping layer into the first conductive material.

18. The method of claim 1 , wherein the capping layer is a layer of the second conductive material.

19. The method of claim 1 , wherein the first conductive feature is free of the second conductive material.

20. The method of claim 13 , wherein the third metal region physically contacts the insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2021
From: LAI, BO-YU; LEE, CHIN-SZU; WU, SZU-HUA; LIANG, SHUEN-SHIN; CHU, CHIA-HUNG; LIN, KENG-CHU; WANG, SUNG-LI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 057170/0463 →
Continuity (2)
Provisional Application 63154019 · Feb 26, 2021
Related Publication 20220277994A1 · Sep 1, 2022
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