Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same
Memory dies on a wafer may include multiple memory blocks including bit lines extending along different directions. A memory die may include a first-type plane including first memory blocks and a second-type plane including second memory blocks. In this case, memory blocks having different bit line directions may be formed within a same memory die. An exposure field may include multiple types of memory dies that are oriented in different orientations. The bit line directions may be oriented differently in the multiple types of memory dies. Each lithographic exposure process may include a first step in which lithographic patterns in first exposure fields are oriented in one direction, and a second step in which lithographic patterns in second exposure fields are oriented in another direction. The different orientations of bit lines and word lines may change local directions of stress to reduce wafer distortion.
1. A memory die comprising:
a first plane including a plurality of first memory blocks; and
a second plane including a plurality of second memory blocks,
wherein:
each memory block respectively selected from the plurality of first memory blocks and the plurality of second memory blocks includes a respective set of memory stack structures that vertically extend through a respective alternating stack of insulating layers and electrically conductive layers, wherein each memory stack structure within the sets of memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;
each of the first plane includes a respective set of first bit lines that laterally extend along a first horizontal direction and electrically connected to a respective subset of vertical semiconductor channels; and
each of the second plane includes a respective set of second bit lines that are parallel with respect to one another and laterally extend along a second horizontal direction that is perpendicular to the first horizontal direction and electrically connected to a respective subset of vertical semiconductor channels within the second plane.
2. The memory die of claim 1 , wherein:
electrically conductive layers within the first plane comprise word lines for a respective one of the first memory blocks and laterally extend along the second horizontal direction; and
electrically conductive layers within the second plane comprise word lines for a respective one of the second memory blocks and laterally extend along the first horizontal direction.
3. The memory die of claim 2 , wherein:
first memory blocks within each first plane are laterally spaced apart with respect to one another by first trenches that laterally extend along the second horizontal direction;
second memory blocks within each second plane are laterally spaced apart with respect to one another by second trenches that laterally extend along the first horizontal direction;
each of the first bit lines extends over a respective plurality of first memory blocks; and
each of the second bit lines extends over a respective plurality of second memory blocks.
4. The memory die of claim 1 , wherein the semiconductor die comprises:
a pair of first sidewalls that are parallel to the first horizontal direction;
a pair of second sidewalls that are parallel to the second horizontal direction;
a planar top surface adjoined to an upper edge of each of the pair of first sidewalls; and
a planar bottom surface adjoined to a lower edge of each of the pair of second sidewalls.
5. The memory die of claim 1 , wherein:
the memory die includes a same total number of the first plane as a total number of the second plane; and
memory stack structures within each of the second plane has a layout that is rotated from a layout of memory stack structures within one of the first plane by 90 degrees or 270 degrees.