IP Library › Granted Patent US 11,681,348
Granted Patent B2
US 11,681,348 · App. 16/403,411 · Granted Jun 20, 2023

High speed / low power server farms and server networks

Inventor: L. Pierre de Rochemont (Austin, TX)
G06F1/324G05B9/02
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Quick Facts
Patent No.
US 11,681,348
App. No.
16/403,411
Granted
Jun 20, 2023
Kind
B2
Abstract

A server farm has servers with at least one hybrid computing module operating at a system clock speed that optimally matches the intrinsic clock speed of a semiconductor die embedded within a high speed semiconductor chip stack or mounted upon the semiconductor carrier.

Claims (8)

1. A server farm comprising a server, wherein the server or servers comprise:

at least one hybrid computing module operating at a system clock speed that optimally matches an intrinsic clock speed of a semiconductor die embedded within a high speed semiconductor chip stack or mounted upon a semiconductor carrier; and

one or more high-speed semiconductor chip stacks bonded to the surface of a semiconductor carrier in which at least one passive component element maintains critical performance tolerances, and has a polarization response time determined solely by orbital deformations and operates in phase, thus does not distort, any of an applied signal components forming a high-speed digital pulse operating at clock speeds up to and into a terahertz (THz) frequency domain.

2. A server farm as in claim 1 , wherein the hybrid computing module within a server or plurality of servers comprises a power management device that further comprises a resonant gate transistor.

3. The server farm of claim 2 , wherein the hybrid computing module is configured for Minimal Instruction Set Computing by means of a chip that comprises a FORTH engine mounted on a semiconductor carrier or embedded within a high speed chip stack.

4. The server farm of claim 2 , wherein the hybrid computing module configured for Minimal Instruction Set Computing utilizes a computing language other than FORTH, but the processor chip that enables the engine to adopt a Stack Machine Architecture has features similar to a FORTH engine including:

the ability to access multiple memory spaces simultaneously in a single microprocessor clock cycle; and,

that utilizes a minimal number of instruction sets through the use of separate buses to access memory holding a data stack, a return stack, and a program memory, among other useful program utilities.

Continuity (2)
Provisional Application 62666124 · May 3, 2018
Related Publication 20200033931A1 · Jan 30, 2020
Cited By (6)
US 12,332,717 US 12,489,530 US 12,578,778 US 12,585,320 US 12,669,857 US 12,717,396