Planar surface mount micro-LED for fluidic assembly
Planar surface mount (SM) micro light emitting diodes (μLEDs) are presented. The fabrication method provides a MOCVD LED structure with a stack including a first doped semiconductor in a first plane, a MQW layer overlying the first doped semiconductor in a second plane, and a second doped semiconductor overlying the MQW layer in a third plane. An electrical insulator is conformally deposited over the etched stack in a fourth plane, and etched to expose the second doped semiconductor, creating a first via. Etching exposes the first doped semiconductor, creating a second via. A first electrode is connected to the second doped semiconductor through the first via, and has a substrate interface surface in a fifth plane with an average planarity tolerance of less than 10 nanometers. A second electrode is connected to the first doped semiconductor through the second via, and has a substrate interface surface in the fifth plane.
1. A planar surface mount (SM) center emission micro-light emitting diode (μLED) comprising:
a first doped semiconductor formed as a base and doped with a dopant selected from the dopant group consisting of n and p dopants, the first doped semiconductor comprising a planar bottom surface and a center plateau formed in a top surface first plane separated from a perimeter formed in the top surface first plane;
a multiple quantum well (MQW) layer having a top surface formed in a second plane overlying the first doped semiconductor center plateau and perimeter;
a second doped semiconductor doped with the unselected dopant from the dopant group, formed as a layer having a top surface in a third plane overlying the MQW layer;
an electrical insulator having a first portion formed as a layer with a top surface in a fourth plane overlying the second doped semiconductor, and a second portion overlying a perimeter trench valley segmenting the perimeter with a top surface in a plane located between the first plane and the fourth plane;
a first electrode overlying the center plateau, connected to the second doped semiconductor by a center via through the electrical insulator first portion, and having a substrate interface surface in a fifth plane; and,
a second electrode having a first portion with a substrate interface surface formed on the electrical insulator second portion and connected to the first doped semiconductor by a perimeter via formed through the electrical insulator, and a second portion overlying a perimeter of the electrical insulator first portion and having a substrate interface surface in the fifth plane.
2. The SM center emission μLED of claim 1 further comprising:
a trench moat formed in the first doped semiconductor separating the center plateau from the perimeter;
wherein the trench moat and perimeter trench valley have top surfaces formed in a sixth plane underlying the first plane.
3. The SM center emission μLED of claim 1 wherein the first and second doped semiconductors are doped gallium nitride (GaN).
4. The SM center emission μLED of claim 1 wherein the first and second doped semiconductors are selected from the group consisting of p-doped gallium phosphide (p-GaP) or n-doped gallium indium phosphide (n-GaInP).
5. The SM center emission μLED of claim 1 further comprising:
a plurality of first doped semiconductor perimeter segments separated by a plurality of perimeter trench valleys;
wherein the MQW layer, second doped semiconductor, and electrical insulator first portion overlie each first doped semiconductor perimeter segment; and,
wherein the second electrode first portion is formed on each perimeter trench valley and connected to the first doped semiconductor through a corresponding perimeter via, and wherein the second electrode second portion overlies segmented perimeters of the electrical insulator first portion with a substrate interface surface in the fifth plane.
6. The SM center emission μLED of claim 1 wherein the first doped semiconductor, MQW layer, and second doped semiconductor form an etched stack having a height orthogonal to the first, second, and third planes of less than 2 microns; and,
wherein the average planarity tolerance of the first and second electrode interfaces in the fifth plane is less than 10 nanometers.
7. The SM center emission μLED of claim 1 wherein the first doped semiconductor base has a circular perimeter.
8. The SM center emission μLED of claim 1 wherein the first and second electrode interface surfaces include a solder layer made from an alloy selected from the group consisting of indium/tin (In/Sn) and gold/germanium (Au/Ge).
9. The SM center emission μLED of claim 1 wherein the substrate interface surfaces of the first and second electrodes are gold.
10. The SM center emission μLED of claim 1
further comprising:
a navigation keel attached to the first doped semiconductor base bottom surface.
11. A planar surface mount (SM) perimeter emission micro-light emitting diode (μLED) comprising:
a first doped semiconductor formed as a base and doped with a dopant selected from the dopant group consisting of n and p dopants, the first doped semiconductor comprising a planar bottom surface, and a center plateau formed in a top surface first plane separated from a perimeter formed in the top surface first plane;
a multiple quantum well (MQW) layer having a top surface formed in a second plane overlying the first doped semiconductor center plateau and perimeter;
a second doped semiconductor doped with the unselected dopant from the dopant group and formed as a layer having a top surface in a third plane overlying the MQW layer;
an electrical insulator formed as a layer with a top surface in a fourth plane overlying the second doped semiconductor;
a first electrode overlying the electrical insulator, connected to the first doped semiconductor center plateau by a center via formed through the second doped semiconductor, MQW layer, and electrical insulator, and having a substrate interface surface in a fifth plane; and,
a second electrode overlying a perimeter of the electrical insulator and connected to the second doped semiconductor by a perimeter via formed through the electrical insulator, and having a substrate interface surface in the fifth plane.
12. The SM perimeter emission μLED of claim 11 further comprising:
a trench moat formed in the first doped semiconductor separating the center plateau from the perimeter, having a top surface formed in a sixth plane underlying the first plane.
13. The SM perimeter emission μLED of claim 11 wherein the first and second doped semiconductors are doped gallium nitride (GaN).
14. The SM perimeter emission μLED of claim 11 wherein the first and second doped semiconductors are selected from the group consisting of p-doped gallium phosphide (p-GaP) or n-doped gallium indium phosphide (n-GaInP).
15. The SM perimeter emission μLED of claim 11 wherein the first doped semiconductor, MQW layer, and second doped semiconductor form an etched stack having a height orthogonal to the first, second, and third planes of less than 2 microns; and,
wherein the average planarity tolerance of the first and second electrode interface surfaces in the fifth plane is less than 10 nanometers.
16. The SM perimeter emission μLED of claim 11 wherein the first doped semiconductor base has a circular perimeter.
17. The SM perimeter emission μLED of claim 11 wherein the first and second electrode interface surfaces include a solder layer made from an alloy selected from the group consisting of indium/tin (In/Sn) and gold/germanium (Au/Ge).
18. The SM perimeter emission μLED of claim 11 wherein the substrate interface surfaces of the first and second electrodes are gold.
19. The SM perimeter emission μLED of claim 11
further comprising:
a navigation keel attached to the first doped semiconductor base bottom surface.
20. A planar surface mount (SM) full area emission micro-light emitting diode (μLED) comprising:
a first doped semiconductor formed as a base and doped with a dopant selected from the dopant group consisting of n and p dopants, the first doped semiconductor having a top surface formed in a first plane comprising a plateau;
a multiple quantum well (MQW) layer having a top surface formed in a second plane overlying the first doped semiconductor plateau;
a second doped semiconductor doped with the unselected dopant from the dopant group and formed as a layer having a top surface in a third plane overlying the MQW layer;
an electrical insulator with a first portion formed as a layer with a top surface in a fourth plane overlying the second doped semiconductor, and a second portion overlying a first doped semiconductor perimeter trench valley with a top surface located in a plane between the first plane and the fourth plane;
a first electrode overlying the plateau, connected to the second doped semiconductor by a plateau via formed through the electrical insulator first portion, and having a substrate interface surface in a fifth plane; and,
a second electrode having a first portion with a substrate interface surface formed on the electrical insulator second portion and connected to the first doped semiconductor by a perimeter via formed through the electrical insulator, and a second portion formed overlying a perimeter of the electrical insulator first portion with a substrate interface surface in the fifth plane.
21. The SM full area emission μLED of claim 20 wherein the first doped semiconductor perimeter trench valley has a top surface formed in a sixth plane underlying the first plane.
22. The SM full area emission μLED of claim 20 wherein the first and second doped semiconductors are doped gallium nitride (GaN).
23. The SM full area emission μLED of claim 20 wherein the first and second doped semiconductors are selected from the group consisting of p-doped gallium phosphide (p-GaP) or n-doped gallium indium phosphide (n-GaInP).
24. The SM full area emission μLED of claim 20 further comprising:
a plurality of first doped semiconductor perimeter trench valleys; and,
wherein the second electrode first portion is formed on each perimeter trench valley and connected to the first doped semiconductor through a corresponding perimeter via, and wherein the second electrode second portion overlies perimeter segments of the electrical insulator first portion with a substrate interface surface in the fifth plane.
25. The SM full area emission μLED of claim 20 wherein the first doped semiconductor, MQW layer, and second doped semiconductor form an etched stack having a height orthogonal to the first, second, and third planes of less than 2 microns; and,
wherein the average planarity tolerance of the first and second electrode interface surfaces in the fifth plane is less than 10 nanometers.
26. The SM full area emission μLED of claim 20 wherein the first doped semiconductor base has a circular perimeter.
27. The SM full area emission μLED of claim 20 wherein the first and second electrode interface surfaces include a solder layer made from an alloy selected from the group consisting of indium/tin (In/Sn) and gold/germanium (Au/Ge).
28. The SM full area emission μLED of claim 20 wherein the substrate interface surfaces of the first and second electrodes are gold.
29. The SM full area emission μLED of claim 20 wherein the first doped semiconductor base has a bottom surface; and,
the SM full area emission μLED further comprising:
a navigation keel attached to the first doped semiconductor base bottom surface.
30. A method for fabricating a surface mount (SM) micro light emitting diode (μLED), the method comprising:
providing a metalorganic chemical vapor deposition (MOCVD) LED structure comprising a growth substrate, a stack overlying the growth substrate comprising a first doped semiconductor with a top surface in a first plane, a multiple quantum well (MQW) layer overlying the first doped semiconductor having a top surface in a second plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a third plane, where the first and second doped semiconductors are oppositely doped with n and p dopants;
etching the MOCVD structure to form a plurality of singulated dies on the growth substrate;
fabricating a μLED from each die as follows:
selectively etching the MOCVD stack;
conformally depositing an electrical insulator to form a top surface in a fourth plane overlying the etched stack;
selectively etching to expose the second doped semiconductor, creating a first via;
selectively etching to expose the first doped semiconductor, creating a second via;
forming a first electrode overlying the first via, connected to the second doped semiconductor through the first via, and having a substrate interface surface in a fifth plane;
forming a second electrode overlying the second via, connected to the first doped semiconductor through the second via, and having a substrate interface surface in the fifth plane; and,
separating the fabricated μLEDs from the growth substrate.
31. The method of claim 30 wherein the SM μLED is a center emission μLED;
wherein selectively etching the MOCVD stack includes creating a central plateau stack surrounded by a trench moat exposing the first doped semiconductor, and a perimeter stack segmented by a perimeter trench valley exposing the first doped semiconductor;
wherein conformally depositing the electrical insulator overlying the etched stack includes forming the fourth plane overlying the central plateau stack and the perimeter stack;
wherein selectively etching to expose the second doped semiconductor includes etching a portion of the electrical insulator overlying the central plateau stack to create the first via;
wherein selectively etching to expose the first doped semiconductor includes etching the electrical insulator overlying the perimeter trench valley to create the second via;
wherein forming the first electrode includes forming the first electrode overlying the central plateau stack and connected to the second doped semiconductor through the first via; and,
wherein forming the second electrode includes forming a second electrode having a first portion formed on the perimeter trench valley and connected to the first doped semiconductor through the second via, and a second portion overlying the electrical insulator formed on the perimeter stack and having a substrate interface surface in the fifth plane.
32. The method of claim 30 wherein the SM μLED is a perimeter emission μLED;
wherein selectively etching the stack includes creating a central plateau stack separated from a perimeter stack by a trench moat exposing the first doped semiconductor;
wherein conformally depositing the electrical insulator includes forming the fourth plane overlying the central plateau stack and the perimeter stack;
wherein selectively etching to expose the second doped semiconductor includes etching a portion of the electrical insulator overlying the perimeter stack to expose the second doped semiconductor;
wherein selectively etching to expose the first doped semiconductor includes etching a portion of the electrical insulator, as well as underlying portions of second doped semiconductor and MQW layer in the central plateau stack, to expose the first doped semiconductor;
wherein forming the first electrode includes forming the first electrode overlying the electrical insulator formed on the perimeter stack, and connected to the second doped semiconductor through the first via; and,
wherein forming the second electrode includes forming the second electrode overlying the central plateau stack and connected to the first doped semiconductor through the second via.
33. The method of claim 30 wherein the SM μLED is a full area emission μLED;
wherein selectively etching the MOCVD stack includes forming a plateau stack and a perimeter trench valley in the plateau stack exposing the first doped semiconductor;
wherein selectively etching to expose the second doped semiconductor includes etching a portion of the electrical insulator overlying the plateau stack to expose the second doped semiconductor;
wherein selectively etching to expose the first doped semiconductor includes etching electrical insulator overlying the perimeter trench valley;
wherein forming the first electrode includes forming the first electrode overlying the plateau stack and connected to the second doped semiconductor through the first via; and,
wherein forming the second electrode includes forming a first portion of the second electrode overlying the perimeter trench via and connected to the first doped semiconductor through the second via, and a second portion overlying the electrical insulator formed on a perimeter of the plateau stack and having a substrate interface surface in the fifth plane.
34. The method of claim 30 wherein separating fabricated μLEDs from the growth substrate includes forming μLEDs having a maximum cross-section co-planar with the first, second, and third planes of 150 microns, a plateau stack height orthogonal to the first, second, and third planes of less than 2 microns, and an average fifth plane planarity tolerance of less than 10 nanometers.