Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
1. An integrated circuit structure, comprising:
a fin comprising silicon;
a gate electrode over the fin;
a first source or drain region in the fin proximate a first side of the gate electrode, the first source or drain region comprising two or more facets and a top surface, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a first germanide layer over the top surface of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second source or drain region in the fin proximate a second side of the gate electrode opposite the first side, the second source or drain region comprising two or more facets and a top surface, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%; and
a second germanide layer over the top surface of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium.
2. The integrated circuit structure of claim 1 , wherein the first and second source or drain regions have a boron concentration greater than 1E20.
3. The integrated circuit structure of claim 1 , wherein the first and second source or drain regions have a boron concentration graded from a base level to a concentration in excess of 1E20.
4. The integrated circuit structure of claim 1 , wherein the fin comprises a strained channel between the first and second source or drain regions.
5. The integrated circuit structure of claim 1 , wherein the first and second source or drain regions are P-type.
6. An integrated circuit structure, comprising:
a body comprising silicon;
a gate electrode over the body;
a first source or drain region in the body proximate a first side of the gate electrode, the first source or drain region comprising two or more facets and a top surface, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a first germanide layer over the top surface of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second source or drain region in the body proximate a second side of the gate electrode opposite the first side, the second source or drain region comprising two or more facets and a top surface, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%; and
a second germanide layer over the top surface of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium.
7. The integrated circuit structure of claim 6 , wherein the first and second source or drain regions have a boron concentration greater than 1E20.
8. The integrated circuit structure of claim 6 , wherein the first and second source or drain regions have a boron concentration graded from a base level to a concentration in excess of 1E20.
9. The integrated circuit structure of claim 6 , wherein the body comprises a strained channel between the first and second source or drain regions.
10. The integrated circuit structure of claim 6 , wherein the first and second source or drain regions are P-type.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin comprising silicon;
a gate electrode over the fin;
a first source or drain region in the fin proximate a first side of the gate electrode, the first source or drain region comprising two or more facets and a top surface, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a first germanide layer over the top surface of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second source or drain region in the fin proximate a second side of the gate electrode opposite the first side, the second source or drain region comprising two or more facets and a top surface, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%; and
a second germanide layer over the top surface of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a camera coupled to the board.
15. The computing device of claim 11 , further comprising:
a global positioning system coupled to the board.
16. The computing device of claim 11 , further comprising:
a battery coupled to the board.
17. The computing device of claim 11 , further comprising:
an antenna coupled to the board.
18. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
19. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
20. The computing device of claim 11 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.