Semiconductor package having thermal conductive pattern surrounding the semiconductor die
Semiconductor packages are provided. One of the semiconductor package includes a semiconductor die, a thermal conductive pattern, an encapsulant and a thermal conductive layer. The thermal conductive pattern is disposed aside the semiconductor die. The encapsulant encapsulates the semiconductor die and the thermal conductive pattern. The thermal conductive layer covers a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.
1. A semiconductor package, comprising:
a semiconductor die;
a thermal conductive pattern aside the semiconductor die;
an encapsulant, encapsulating the semiconductor die and the thermal conductive pattern; and
a thermal conductive layer covering a rear surface of the semiconductor die, wherein the thermal conductive pattern is thermally coupled to the semiconductor die through the thermal conductive layer and electrically insulated from the semiconductor die.
2. The semiconductor package as claimed in claim 1 , further comprising a semiconductor device stacked over and electrically connected to the semiconductor die.
3. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete through vias.
4. The semiconductor package as claimed in claim 3 , wherein the plurality of discrete through vias are arranged along at least one ring-shaped path surrounding the semiconductor die.
5. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a ring-shaped structure surrounding the semiconductor die.
6. The semiconductor package as claimed in claim 1 , wherein the thermal conductive pattern comprises a plurality of discrete wall-shaped structures.
7. The semiconductor package as claimed in claim 1 , further comprising a redistribution circuit structure disposed over an active surface of the semiconductor die and a first surface of the encapsulant, wherein the active surface of the semiconductor die is opposite to the rear surface of the semiconductor die, and the redistribution circuit structure is electrically connected to the semiconductor die.
8. The semiconductor package as claimed in claim 7 , wherein the redistribution circuit structure further comprises a dummy pattern disposed on the first surface of the encapsulant and the thermal conductive pattern is connected to the dummy pattern.
9. The semiconductor package as claimed in claim 1 , wherein the thermal conductive layer extends outwardly from the rear surface of the semiconductor die to partially cover the encapsulant.
10. A semiconductor package, comprising:
a semiconductor die;
an encapsulant laterally encapsulating the semiconductor die;
a first through via embedded in the encapsulant and electrically connected to the semiconductor die;
a second through via embedded in the encapsulant and electrically insulated from the semiconductor die; and
a thermal conductive layer covering the semiconductor die, wherein the second through via is thermally coupled to the semiconductor die through the thermal conductive layer.
11. The semiconductor package as claimed in claim 10 , further comprising a semiconductor device stacked over and electrically connected to the semiconductor die, wherein the thermal conductive layer and the semiconductor device are separated by a distance.
12. The semiconductor package as claimed in claim 10 , wherein the thermal conductive layer is disposed over the semiconductor die and extends onto the second through via.
13. The semiconductor package as claimed in claim 10 , wherein the thermal conductive layer is in contact with the semiconductor die and the second through via.
14. The semiconductor package as claimed in claim 10 , wherein the thermal conductive layer comprises a first portion covering the semiconductor die and a second portion covering the encapsulant, and the first portion is thicker than the second portion.
15. The semiconductor package as claimed in claim 10 , wherein a first minimum distance between the first through via and the semiconductor die is less than a second minimum distance between the second through via and the semiconductor die.
16. A semiconductor package, comprising:
a semiconductor die;
an encapsulant laterally encapsulating the semiconductor die;
a first through via embedded in the encapsulant and electrically connected to the semiconductor die;
a second through via embedded in the encapsulant and electrically insulated from the semiconductor die; and
a thermal conductive layer covering the semiconductor die and the encapsulant, wherein the thermal conductive layer comprises a first portion covering the semiconductor die and a second portion covering the second through via, and the first portion of the thermal conductive layer is thicker than the second portion of the thermal conductive layer.
17. The semiconductor package as claimed in claim 16 , wherein the thermal conductive layer partially covers the encapsulant.
18. The semiconductor package as claimed in claim 16 , wherein a first minimum distance between the first through via and the semiconductor die is greater than a second minimum distance between the second through via and the semiconductor die.
19. The semiconductor package as claimed in claim 16 , wherein a width of the second through via ranges from one half to two times of a width of the first through via.
20. The semiconductor package as claimed in claim 16 , wherein the thermal conductive layer is in contact with second through via.