IP Library Granted Patent US 10,658,383
Granted Patent B2
US 10,658,383 · App. 16/519,705 · Granted May 19, 2020

Nonvolatile semiconductor memory device and method for manufacturing same

Inventors: Yoshiaki Fukuzumi (Kanagawa, JP); Ryota Katsumata (Kanagawa, JP); Masaru Kito (Kanagawa, JP); Masaru Kidoh (Tokyo, JP); Hiroyasu Tanaka (Tokyo, JP); Yosuke Komori (Kanagawa, JP); Megumi Ishiduki (Kanagawa, JP); Junya Matsunami (Kanagawa, JP); Tomoko Fujiwara (Kanagawa, JP); Hideaki Aochi (Kanagawa, JP); Ryouhei Kirisawa (Kanagawa, JP); Yoshimasa Mikajiri (Kanagawa, JP); Shigeto Oota (Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11582H01L21/223H01L21/265H01L27/11578H01L29/04H01L29/1037H01L29/16H01L29/42344H01L29/4916H01L29/66666H01L29/66833H01L29/7827H01L29/792H01L29/7926
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Quick Facts
Patent No.
US 10,658,383
App. No.
16/519,705
Granted
May 19, 2020
Kind
B2
Abstract

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Claims (23)

1. A method for manufacturing a nonvolatile semiconductor memory device,

the nonvolatile semiconductor memory device comprising:

a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction;

a selection gate electrode stacked on the stacked structural unit in the first direction;

an insulating layer stacked on the selection gate electrode in the first direction;

a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction;

a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and

a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit,

the method comprising:

forming the stacked structural unit including the insulating film alternately stacked with the electrode film on a major surface of a substrate;

forming the selection gate electrode on the stacked structural unit;

forming the insulating layer on the selection gate electrode;

making a first through-hole piercing at least the selection gate electrode and the insulating layer in the first direction perpendicular to the major surface and forming a first semiconductor film on an inner side face of the first through-hole;

forming the first core unit on an inner side of the first semiconductor film;

recessing the core unit; and

introducing an impurity into the first semiconductor film.

2. The method according to claim 1 , wherein the introducing of the impurity includes at least one introducing selected from vapor phase diffusion of an impurity or ion implantation.

3. The method according to claim 1 , wherein the introducing of the impurity includes irradiating the impurity on the recessed core unit, causing a travel direction of the impurity to have a component in a direction orthogonal to the first direction, and introducing the impurity into the first semiconductor film.

4. The method according to claim 1 , further comprising filling a conducting material into the first through-hole and onto the first semiconductor film including the introduced impurity to form the first conducting layer in contact with the core unit.

5. The method according to claim 1 , further comprising;

making a second through-hole and a third through-hole, the second through-hole piercing the selection gate electrode in the first direction perpendicular to the major surface, the third through-hole piercing the insulating layer in the first direction to communicate with the second through-hole, a diameter of the third through-hole at an upper end of the insulating layer being larger than a diameter of the second through-hole;

forming a second semiconductor film on an inner side faces of the second through-hole and the third through-hole; and

implanting an impurity into a portion of the second semiconductor film on the selection gate electrode side.

Assignments (3)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
Priority Claims (1)
JP 2009-072950 · Mar 24, 2009 · national
Continuity (7)
Continuation 15915653 · Mar 8, 2018
Continuation 15424532 · Feb 3, 2017
Continuation 15064270 · Mar 8, 2016
Continuation 14833827 · Aug 24, 2015
Continuation 14150504 · Jan 8, 2014
Continuation 12724713 · Mar 16, 2010
Related Publication 20190348437A1 · Nov 14, 2019