Semiconductor memory device for storing multivalued data
Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
1. A semiconductor memory device comprising:
a memory cell array in which memory cells are provided in a matrix, the memory cells connected to word lines and bit lines, the memory cells storing one of n values (n is a natural number equal to or larger than 3);
data holding circuits connected to the bit lines and holding data read from the memory cells; and
a control circuit configured to control potentials of the word lines and potentials of bit lines,
wherein in a read operation, data in a first memory cell is read and stored to a first data holding circuit, and data in a second memory cell is read and stored to a second data holding circuit at the same time, and
output data from the memory device is determined from the data stored in the first data holding circuit and the second data holding circuit.
2. The semiconductor memory device according to claim 1 , wherein the first memory cell and the second memory cell are connected to a same word line.
3. The semiconductor memory device according to claim 1 , wherein the memory cells are nonvolatile memory cells.
4. The semiconductor memory device according to claim 1 , wherein each of the word lines extends in a first direction, and each of the bit lines extends in a second direction crossing the first direction.
5. The semiconductor memory device according to claim 1 , wherein each of the memory cells includes a floating gate and a control gate, physically separated from each other.
6. The semiconductor memory device according to claim 1 , wherein
after a writing of the data is performed to the memory cells and a verification for writing of data of (k−1) value (k≤n) is performed according to the data of the data holding circuits,
a verification for writing of data of k value is performed using a first level corresponding to a value less than the k value and a second level corresponding to the k value,
when a threshold voltage of the memory cell does not reach the first level, the data of the data holding circuit is not changed,
when the threshold voltage of the memory cell reaches the first level and does not reach the second level, the data of the data hold circuit is set as the data of the (k−1) value, and
when the threshold voltage of the memory cell reaches the second level, the data of the data hold circuit is set as non-write data,
a writing of the data is performed to the memory cells according to the data of the data hold circuits after the verification of the k value.
7. A semiconductor memory device comprising:
a memory cell array in which memory cells are provided in a matrix, the memory cells connected to word lines and bit lines, the memory cells storing one of n values (n is a natural number equal to or larger than 3);
data holding circuits connected to the bit lines and holding data read from the memory cells; and
a control circuit configured to control potentials of the word lines and potentials of bit lines,
wherein
the control circuit performs:
a first operation of, in a read operation, reading data in a first memory cell and causing a first data holding circuit to store the read data, and reading data in a second memory cell and causing a second data holding circuit to store the read data, at the same time, and
a second operation of determining output data from the memory device based on the data stored in the first data holding circuit and the date stored in the second data holding circuit.
8. A method for controlling a semiconductor memory device,
the semiconductor memory device comprising:
a memory cell array in which memory cells are provided in a matrix, the memory cells connected to word lines and bit lines, the memory cells storing one of n values (n is a natural number equal to or larger than 3);
data holding circuits connected to the bit lines and holding data read from the memory cells; and
a control circuit configured to control potentials of the word lines and potentials of bit lines,
the method comprising:
wherein in a read operation, reading data in a first memory cell and causing a first data holding circuit to store the read data, and reading data in a second memory cell and causing a second data holding circuit to store the read data, at the same time, and
determining output data from the memory device based on the data stored in the first data holding circuit and the date stored in the second data holding circuit.