Three-dimensional NOR array including active region pillars and method of making the same
A semiconductor structure includes vertically-alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart from each other by line trenches. Laterally-alternating sequences of semiconductor region assemblies and dielectric pillar structures are located within a respective one of the line trenches. Memory films are located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences. Each of the semiconductor region assemblies includes a source pillar structure, a drain pillar structure, and a channel structure including a pair of lateral semiconductor channels that laterally connect the source pillar structure and the drain pillar structure. The memory films may include a charge storage layer or a ferroelectric material layer.
1. A semiconductor structure comprising:
vertically-alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart from each other by line trenches;
laterally-alternating sequences of semiconductor region assemblies and dielectric pillar structures located within a respective one of the line trenches; and
memory films located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences, wherein each of the semiconductor region assemblies comprises:
a respective first active region pillar structure extending through each level of the electrically conductive strips;
a respective second active region pillar structure extending through each level of the electrically conductive strips and laterally spaced from the respective first active region pillar structure, one of the respective first active region pillar structure and the respective second active region pillar structure being a source pillar structure and another of the respective first active region pillar structure and the respective second active region pillar structure being a drain pillar structure;
a respective channel structure including a pair of lateral semiconductor channels that laterally connect the respective first active region pillar structure and the respective second active region pillar structure; and
a respective dielectric core having a pair of first vertical sidewalls that are parallel to a lengthwise direction of the line trenches and a pair of second vertical sidewalls that are perpendicular to the lengthwise direction of the line trenches, wherein the respective channel structure laterally surrounds the respective dielectric core and contacts the pair of first vertical sidewalls of the respective dielectric core and contacts the pair of second vertical sidewalls of the respective dielectric core.
2. The semiconductor structure of claim 1 , wherein each of the lateral semiconductor channels vertically extends continuously through each level of the electrically conductive strips within the vertically-alternating stacks.
3. The semiconductor structure of claim 1 , wherein:
each of the line trenches and the lateral semiconductor channels laterally extends along a first horizontal direction; and
each of the channel structures further comprises a pair of widthwise vertical channel plates that laterally extend along a second horizontal direction and contacts a respective one of the first active region pillar structures and the second active region pillar structures.
4. The semiconductor structure of claim 1 , wherein each of the channel structures further comprises a respective horizontal channel plate located underneath a horizontal plane including bottom surfaces of bottommost electrically conductive strips of the vertically-alternating stacks.
5. The semiconductor structure of claim 1 , further comprising:
first access lines that are parallel to each other and underlying the laterally alternating sequences; and
first connection via structures contacting a respective one of the first access lines and a respective one of the first active region pillar structures.
6. The semiconductor structure of claim 5 , further comprising:
second access lines that are parallel to each other and overlying the vertically-alternating stacks and the laterally alternating sequences; and
second connection via structures contacting a respective one of the second access lines and a respective one of the second active region pillar structures.
7. The semiconductor structure of claim 6 , wherein:
the line trenches laterally extend along a first horizontal direction;
the first access lines extend along a first lengthwise direction that is horizontal and is parallel to the first horizontal direction; and
the second access lines extend along a second lengthwise direction that is horizontal and is perpendicular to the first lengthwise direction.
8. The semiconductor structure of claim 1 , wherein at least one dielectric pillar structure within each line trench laterally contacts a respective first active region pillar structure and a respective second active region pillar structure.
9. The semiconductor structure of claim 1 , wherein each of the memory films comprises a respective layer stack that includes, from one side to another, a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer.
10. The semiconductor structure of claim 1 , wherein each of the memory films comprises a ferroelectric material layer.
11. The semiconductor structure of claim 1 , wherein each of the memory films contacts a plurality of channel structures in a laterally-alternating sequence of semiconductor region assemblies and dielectric pillar structures that is located within a respective one of the line trenches.
12. The semiconductor structure of claim 1 , wherein each of the memory films contacts only a single channel structure within a laterally-alternating sequence of semiconductor region assemblies and dielectric pillar structures that is located within a respective one of the line trenches.
13. The semiconductor structure of claim 1 , wherein the respective channel structure further comprises a pair of widthwise vertical channel plates that laterally extend along a horizontal direction that is perpendicular to the lengthwise direction of the line trenches.
14. The semiconductor structure of claim 13 , wherein:
one the pair of widthwise vertical channel plates contacts a sidewall of one the first active region pillar structures; and
another of the pair of widthwise vertical channel plates contacts a sidewall of one of the second active region pillar structures.
15. The semiconductor structure of claim 13 , wherein the a pair of widthwise vertical channel plates vertically extends at least from a horizontal plane including bottom surfaces of the bottommost electrically conductive strips within the vertically-alternating stacks and at least to a horizontal plane including topmost surfaces of the topmost electrically conductive strips within the vertically-alternating stacks.
16. The semiconductor structure of claim 13 , wherein each of the pair of widthwise vertical channel plates of the respective channel structure is adjoined to a respective pair of vertically-extending edges of the pair of lateral semiconductor channels of the respective channel structure.
17. The semiconductor structure of claim 1 , wherein the pair of widthwise vertical channel plates of the respective channel structure and the pair of lateral semiconductor channels of the respective channel structure have a same material composition and a same lateral thickness.
18. The semiconductor structure of claim 1 , wherein all sidewall surfaces of the respective dielectric core contacts a respective one of inner sidewalls of the respective channel structure.
19. The semiconductor structure of claim 1 , wherein:
the respective channel structure comprises a horizontally-extending semiconductor material portion adjoined to bottom edges of the pair of lateral semiconductor channels and having a same material composition as the pair of lateral semiconductor channels; and
the respective dielectric core contacts an entirety of a top surface of the horizontally-extending semiconductor material portion.