Granted Patent B2

US 12,219,756 · App. 17/664,550 · Granted Feb 4, 2025

Inventors: Peter Rabkin (Cupertino, CA); Masaaki Higashitani (Cupertino, CA)

Assignee: SANDISK TECHNOLOGIES LLC

H10B41/27H01L23/5226H10B41/10H10B41/35H10B43/10H10B43/27H10B43/35

Abstract

Claims (44)

1. A memory device comprising:

at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate;

a memory opening vertically extending through the at least one instance of the unit layer stack; and

a memory opening fill structure located in the memory opening and comprising a control gate electrode and a memory film in contact with each instance of the semiconductor channel, wherein the memory film comprises a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer.

2. The memory device of claim 1 , wherein the barrier layer comprises a dielectric blocking barrier layer.

3. The memory device of claim 1 , wherein the resonant tunneling barrier stack comprises at least two semiconductor quantum wells.

4. The memory device of claim 3 , wherein:

the at least two semiconductor quantum wells comprise a first quantum well and a second quantum well located between the first quantum well and the control gate electrode;

the first quantum well comprises a first semiconductor well layer located between a first barrier layer and a second barrier layer; and

the second quantum well comprises a second semiconductor well layer located between the second barrier layer and a third barrier layer.

5. The memory device of claim 4 , wherein the first semiconductor well layer is thinner than the second semiconductor well layer.

6. The memory device of claim 5 , wherein the first semiconductor well layer and the second semiconductor well layer have a narrower bandgap than the first, second, and third barrier layers.

7. The memory device of claim 6 , wherein the first semiconductor well layer and the second semiconductor well layer comprise indium arsenide, and the first, second, and third barrier layers comprise aluminum antimonide.

8. The memory device of claim 2 , wherein:

the memory material layer comprises a dielectric charge storage material;

the semiconductor channel comprises a first compound semiconductor material; and

the dielectric blocking barrier layer comprises a dielectric oxide material.

9. The memory device of claim 8 , wherein the memory material layer comprises a silicon nitride layer and the semiconductor channel comprises an indium arsenide layer.

10. The memory device of claim 2 , wherein the dielectric blocking barrier layer comprises a dielectric metal oxide layer.

11. The memory device of claim 10 , wherein the dielectric blocking barrier layer further comprises a silicon oxide layer in contact with the dielectric metal oxide layer.

12. The memory device of claim 10 , wherein the dielectric metal oxide layer contacts the memory material layer.

13. The memory device of claim 2 , wherein:

the dielectric blocking barrier layer is surrounded by the memory material layer; and

the memory material layer is surrounded by the resonant tunneling barrier stack.

14. The memory device of claim 13 , wherein the resonant tunneling barrier stack is laterally surrounded by and contacts each semiconductor channel within the at least one instance of the unit layer stack.

15. A method of operating the three-dimensional memory device of claim 1 , comprising:

applying a positive voltage to the control gate electrode to program a data bit in the memory material layer; and

applying a positive voltage to the semiconductor channel to erase the data bit in the memory material layer.

16. A method of making a memory device, comprising:

forming at least one instance of a unit layer stack including a source-level material layer, a channel-level material layer, and a drain-level material layer over a substrate, wherein the source-level material layer and the drain-level material layer are formed as, or are subsequently replaced with, an electrically conductive source layer and an electrically conductive drain layer, and wherein the channel-level material layer comprises a semiconductor channel or is replaced with the semiconductor channel;

forming a memory opening through the at least one instance of the unit layer stack;

forming a memory film in the memory opening, wherein the memory film comprises a layer stack that includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer; and

forming a control gate electrode on an inner sidewall of the memory film.

17. The method of claim 16 , wherein the barrier layer comprises at least one dielectric oxide material.

18. The method of claim 17 , wherein the barrier layer further comprises a silicon oxide layer.

19. The method of claim 16 , wherein:

the resonant tunneling barrier stack is formed directly on a sidewall of the memory opening; and

the control gate electrode is formed directly on the barrier layer.

20. The method claim 16 , wherein:

the resonant tunneling barrier stack comprises at least two semiconductor quantum wells;

the least two semiconductor quantum wells comprise a first quantum well and an second quantum well that is formed between the first quantum well and the control gate electrode;

the first quantum well comprises a first semiconductor well layer that is formed between a first barrier layer and a second barrier layer;

the second quantum well comprises a second semiconductor well layer that is formed between the second barrier layer and a third barrier layer; and

the first semiconductor well layer is thinner than the second semiconductor well layer.

Assignments (4)

Continuity (3)

References Cited (30)