Test access mechanism controller including instruction register, instruction decode circuitry
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
1. A test access mechanism controller comprising:
A. a controller clock input, a scan in input coupled to a wrapper serial in output and coupled to a comparator scan in output, and a scan out output coupled to a wrapper scan out input and coupled to a comparator scan out input;
B. an instruction register having an instruction bus input, an instruction output, and a register clock input coupled to the controller clock input;
C. instruction decode circuitry having:
i. an instruction input connected to the instruction output;
ii. mode inputs;
iii. a select input;
iv. a wrapper register clock output;
v. a count clock output;
vi. a compare clock output;
vii. a shift clock output;
viii. a stimulus data clock output;
ix. an expected data clock output; and
x. a mask data clock output.
2. The test access mechanism controller of claim 1 including a test wrapper architecture having:
a wrapper serial input,
a wrapper serial output,
a wrapper clock input,
a capture wrapper input connected to the capture wrapper output,
a shift wrapper input connected to the shift wrapper output,
an update wrapper input connected to the update wrapper output,
a transfer data register input connected to the transfer data register output, and
a select wrapper instruction register input connected to the select wrapper instruction register output.
3. The test access mechanism controller of claim 2 including core circuitry connected to the test wrapper architecture.
4. The test access mechanism controller of claim 1 including gating circuitry having an input coupled to the controller clock input, an input coupled to the wrapper register clock output, and having a gated wrapper register clock output.
5. The test access mechanism controller of claim 1 including gating circuitry having an input coupled to the controller clock input, an input coupled to the count clock output, and having a gated count clock output.
6. The test access mechanism controller of claim 1 including gating circuitry having an input coupled to the controller clock input, an input coupled to the compare clock output, and having a gated compare clock output.
7. The test access mechanism controller of claim 1 including gating circuitry having an input coupled to the controller clock input, an input coupled to the shift clock output, and having a gated shift clock output.
8. The test access mechanism controller of claim 1 including gating circuitry having an input coupled to the controller clock input, an input coupled to the stimulus data clock output, and having a gated stimulus data clock output.
9. The test access mechanism controller of claim 1 including gating circuitry having an input coupled to the controller clock input, an input coupled to the expected data clock output, and having a gated expected data clock output.
10. The test access mechanism controller of claim 1 including gating circuitry having an input coupled to the controller clock input, an input coupled to the mask data clock output, and having a gated mask data clock output.
11. The test access mechanism controller of claim 1 including multiplexing circuitry having an input coupled to the wrapper serial out input, an input coupled to the comparator serial out input, and having the scan out output.
12. The test access mechanism controller of claim 1 in which the instruction decode circuitry has a select wrapper instruction register output.
13. The test access mechanism controller of claim 1 in which the instruction decode circuitry has a shift wrapper output.
14. The test access mechanism controller of claim 1 in which the instruction decode circuitry has a capture wrapper output.
15. The test access mechanism controller of claim 1 in which the instruction decode circuitry has an update wrapper output.
16. The test access mechanism controller of claim 1 in which the instruction decode circuitry has a transfer data register output.