IP Library Granted Patent US 12,610,471
Granted Patent B2
US 12,610,471 · App. 16/854,984 · Granted Apr 21, 2026

Panel-molded electronic assemblies

Inventors: Patrizio Vinciarelli (Boston, MA); Michael B. LaFleur (East Hampstead, NH); Sean Timothy Fleming (Worcester, MA); Rudolph F. Mutter (North Andover, MA); Andrew T. D' Amico (Beverly Hills, CA)
Assignee: Vicor Corporation
H05K3/284B23P15/007B29C45/0055B29C45/14639B29C45/1679H01F27/24H01F27/2804H01R27/02H01R43/205H01R43/24H05K1/0298H05K1/11H05K1/111H05K1/115H05K1/18H05K1/181H05K1/186H05K3/0044H05K3/0052H05K3/007H05K5/0065H05K5/0217H05K5/0247H05K5/04H05K5/064H05K5/065H05K5/10H05K7/1427H05K7/209B29C2045/0058B29C2045/169B29C2793/0009B29C2793/0027B29C2793/009B29K2063/00H01F2027/2809H05K1/0209H05K2201/0183H05K2201/066H05K2201/10303H05K2201/10545H05K2203/1316H05K2203/1327H05K2203/167Y10T29/49117Y10T29/49126Y10T29/4913Y10T29/49133Y10T29/49144Y10T29/49155Y10T29/49158
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,610,471
App. No.
16/854,984
Granted
Apr 21, 2026
Kind
B2
Abstract

A method of encapsulating a panel of electronic components such as power converters reduces wasted printed circuit board area. The panel, which may include a plurality of components, may be cut into one or more individual pieces after encapsulation. The mold may be used to form part of the finished product, e.g. providing heat sink fins or a surface mount solderable surface. Interconnection features provided along boundaries of individual circuits are exposed during the singulation process providing electrical connections to the components without wasting valuable PCB surface area. The molds may include various internal features such as registration features accurately locating the circuit board within the mold cavity, interlocking contours for structural integrity of the singulated module, contours to match component shapes and sizes enhancing heat removal from internal components and reducing the required volume of encapsulant, clearance channels providing safety agency spacing and setbacks for the interconnects. Wide cuts may be made in the molds after encapsulation reducing thermal stresses and reducing the thickness of material to be cut during subsequent singulation. External mold features can include various fin configurations for heat sinks, flat surfaces for surface mounting or soldering, etc. Blank mold panels may be machined to provide some or all of the above features in an on-demand manufacturing system. Connection adapters may be provided to use the modules in vertical or horizontal mounting positions in connector, through-hole, surface-mount solder variations. The interconnects may be plated to provide a connectorized module that may be inserted into a mating connector. Reuseable plates may be used instead of the heat sink panels. Alternatively the panel may be encapsulated in and separated from a re-useable mold after curing.

Claims (94)

1 . A method of making a plurality of electronic devices each device having a plurality of electrical terminals for establishing electrical connections to the device, comprising:

providing a printed circuit board (PCB) panel including a PCB having a plurality of conductive traces and a plurality of components electrically connected to form a plurality of circuits, the PCB having a plurality of embedded conductive features for making electrical connections to the plurality of circuits, wherein the embedded conductive features are embedded within the PCB and unexposed to an environment outside of the PCB prior to cutting of the PCB;

enclosing the PCB panel, including the PCB, components, and embedded conductive features in a mold cavity;

filling the mold cavity with mold compound;

curing the mold compound to form an encapsulated PCB panel that includes cured mold compound on a first side of the PCB panel and a second side of the PCB panel, the embedded conductive features being covered by the cured mold compound on at least one of the first side of the encapsulated PCB panel or the second side of the encapsulated PCB panel; and

cutting the encapsulated PCB panel between the plurality of circuits to form at least one edge of each device and to expose at least a portion of the plurality of embedded conductive features and form respective exposed contacts within the at least one edge;

wherein the cutting cuts through the PCB panel and the cured mold compound on the first and second sides of the PCB panel, and

wherein each of some of the exposed contacts in each device is configured to provide an external power connection or an external control signal connection to a respective circuit within the device.

2 . The method of claim 1 further comprising:

providing one or more registration features for positioning the PCB panel in the mold cavity;

removing the encapsulated PCB panel from a mold that defines the mold cavity; and

creating voids in the mold compound with one or more of the registration features by displacing uncured mold compound for reference after the encapsulated PCB panel is removed from the mold.

3 . The method of claim 1 further comprising:

making holes in the cured mold compound to expose portions of the PCB.

4 . The method of claim 1 further comprising removing a layer of material from a first surface of the encapsulated PCB panel.

5 . The method of claim 4 further comprising removing a layer of material from a second surface of the encapsulated PCB panel.

6 . The method of claim 4 wherein the components include a magnetic core and the removing a layer of material from the first surface of the encapsulated PCB panel exposes a surface of the magnetic core.

7 . The method of claim 6 wherein the removing a layer of material from the first surface of the encapsulated panel assembly provides finished surfaces and reduces the encapsulated panel assembly to a controlled thickness.

8 . The method of claim 1 wherein the cutting divides the PCB panel producing at least one module having a plurality of layers including respective portions of the PCB panel and the cured mold compound on each side of the PCB panel, and the module contains at least one of the circuits.

9 . The method of claim 8 wherein the cutting exposes the embedded conductive features, and the method further comprises

providing an adapter having at least one electrical terminal; and

attaching the at least one electrical terminal to the exposed contacts.

10 . The method of claim 9 wherein

the module comprises a plurality of exposed contacts;

the adapter has a plurality of electrical terminals arranged to match respective ones of the plurality of exposed contacts; and

the adapter is mechanically secured to the module.

11 . The method of claim 8 , wherein the traces and components are electrically connected to form a plurality of separable circuits arranged in a pattern on the PCB; and the cutting divides the PCB panel along spaces between the separable circuits into a plurality of modules each containing at least one respective circuit.

12 . The method of claim 1 , comprising removing the encapsulated PCB panel from a mold that defines the mold cavity.

13 . The method of claim 12 further comprising:

mating the PCB panel with a center plate having an opening for receiving the PCB panel;

covering the opening of the center plate with at least one plate; and

removing the encapsulated PCB panel from mold panels that define the mold cavity;

wherein the enclosing comprises closing the mold panels against the center plate and exerting pressure to force the at least one plate against the center plate; and

wherein the removing comprises removing the at least one plate from the encapsulated PCB panel.

14 . The method of claim 12 further comprising:

mating the PCB panel with a center plate; and

wherein the enclosing comprises closing the mold against the center plate;

wherein the curing bonds the PCB panel to the center plate;

wherein the removing comprises removing the bonded center plate and PCB panel.

15 . The method of claim 1 , comprising forming a panel assembly including mold panels having interior surfaces that define the mold cavity, in which the mold compound fills spaces between the PCB and the interior surfaces.

16 . The method of claim 15 , comprising cutting the mold panels along with cutting the encapsulated PCB panel to form individual modules, in which for each module, an exterior surface of a portion of one of the mold panels forms an exterior surface of the module.

17 . The method of claim 16 in which the exterior surface of the mold panel comprises a plurality of fins.

18 . The method of claim 16 in which the exterior surface of the mold panel comprises a flat surface.

19 . The method of claim 18 in which the flat surface is adapted for a solder joint.

20 . The method of claim 18 in which one or more pins protrude from the flat surface.

21 . The method of claim 16 in which the exterior surface of the mold panel comprises a flat surface having one or more holes in the flat surface.

22 . The method of claim 21 , further comprising inserting a pin into a respective one of the one or more holes.

23 . The method of claim 1 in which some components are distributed symmetrically between both surfaces of the PCB.

24 . The method of claim 1 in which the PCB includes a top surface and a bottom surface and the plurality of components comprise a set of top-side components mounted on the top surface and a set of bottom-side components mounted on the bottom surface, the top-side components include a number, T, of large-footprint components, the bottom-side components include a number, B, of large-footprint components, and the number T is approximately equal to the number B.

25 . The method of claim 24 in which each of most of the top-side large-footprint components shares a respective set of conductive vias with a corresponding one of the bottom-side large-footprint components.

26 . The method of claim 24 in which each of most of the top-side large-footprint components is located in a respective footprint shared by a corresponding one of the bottom-side large-footprint components.

27 . The method of claim 1 in which some components are distributed symmetrically on a surface of the PCB.

28 . The method of claim 1 in which the PCB includes a top surface and the plurality of components comprises a number of large-footprint components mounted on the top surface, and most of the large-footprint components are distributed symmetrically in relation to an axis on the top surface.

29 . The method of claim 28 in which the axis is along a midline of the top surface.

30 . The method of claim 28 in which the axis is defined in relation to a predetermined component.

31 . The method of claim 1 wherein the embedded conductive features are covered by the cured mold compound on both the first side of the PCB panel and the second side of the PCB panel.

32 . The method of claim 1 wherein prior to enclosing the PCB panel in the mold cavity, the embedded conductive features are embedded in, and unexposed on the surface of, the PCB panel.

33 . The method of claim 1 , further comprising electrically connecting each of some of the exposed contacts to respective external circuitry configured to provide power or a control signal.

34 . The method of claim 1 wherein each electrical terminal comprises one or more of the exposed contacts.

35 . A method of manufacturing a plurality of products each product having a plurality of electrical terminals for establishing electrical connections to the product, comprising:

inserting a printed circuit board including a plurality of components into a mold cavity, the printed circuit board having a plurality of embedded conductive features for making electrical connections to the plurality of components, wherein the embedded conductive features are embedded within the printed circuit board and unexposed to an environment outside of the printed circuit board prior to cutting of the printed circuit board;

closing a top mold and a bottom mold that define defines the mold cavity to form a seal around the cavity;

filling the cavity with mold compound having a top portion that covers at least a portion of a top surface of the printed circuit board and a bottom portion that covers at least a portion of a bottom surface of the printed circuit board;

curing the mold compound in the cavity to form an encapsulated panel assembly, the embedded conductive features being covered by the cured mold compound on at least one side of the encapsulated panel assembly; and

cutting the encapsulated panel assembly to separate the plurality of products from the encapsulated panel assembly, the products each including a respective section of the printed circuit board, in which the cutting forms at least one edge of each product and exposes at least a portion of the plurality of embedded conductive features that form exposed contacts within the at least one edge, each separated product includes two or more exposed contacts, and each of some of the exposed contacts in each product is configured to provide an external power connection or an external control signal connection to a respective component within the product.

36 . The method of claim 35 wherein the encapsulated panel assembly includes cured mold compound on a first side of the encapsulated panel assembly and a second side of the encapsulated panel assembly, wherein the embedded conductive features are covered by the cured mold compound on both the first side of the encapsulated panel assembly and the second side of the encapsulated panel assembly.

37 . The method of claim 35 wherein prior to inserting the printed circuit board into the mold cavity, the embedded conductive features are embedded in, and unexposed on the surface of, the printed circuit board.

38 . The method of claim 35 , further comprising electrically connecting each of some of the exposed contacts to respective external circuitry configured to provide power or a control signal.

39 . The method of claim 35 wherein the cutting divides the encapsulated panel assembly producing at least one module having a plurality of layers including respective portions of the panel assembly and the cured mold compound on each side of the panel assembly, and the module contains at least one of the components.

40 . The method of claim 39 wherein the cutting exposes the embedded conductive features, and the method further comprises providing an adapter having at least one electrical terminal; and

attaching the at least one electrical terminal to the exposed contacts.

41 . The method of claim 40 wherein

the module comprises a plurality of exposed contacts;

the adapter has a plurality of electrical terminals arranged to match respective ones of the plurality of exposed contacts; and

the adapter is mechanically secured to the module.

42 . The method of claim 35 wherein each electrical terminal comprises one or more of the exposed contacts.

43 . A method of making a plurality of electronic devices each device having a plurality of electrical terminals for establishing electrical connections to the device, comprising:

providing a printed circuit board (PCB) panel including a PCB having a plurality of conductive traces and a plurality of components electrically connected to form a plurality of circuits, the PCB having a plurality of embedded conductive features for making electrical connections to each of the plurality of circuits, wherein the embedded conductive features are embedded within the PCB and unexposed to an environment outside of the PCB prior to cutting of the PCB;

enclosing the PCB panel, including the PCB, components, and embedded conductive features in a mold cavity;

filling the mold cavity with mold compound;

curing the mold compound to form an encapsulated PCB panel, the embedded conductive features being covered by the cured mold compound on at least one side of the encapsulated PCB panel; and

cutting the encapsulated PCB panel to singulate each of the plurality of circuits from the encapsulated PCB panel to form at least one edge of each device and expose at least a portion of the plurality of embedded conductive features and form respective exposed contacts within the at least one edge in each of the singulated circuits, wherein at least some of the exposed contacts are configured to provide a plurality of power connections, control connections, signal connections, or a combination thereof.

44 . The method of claim 43 wherein the encapsulated PCB panel includes cured mold compound on a first side of the encapsulated PCB panel and a second side of the encapsulated PCB panel, wherein the embedded conductive features are covered by the cured mold compound on both the first side of the encapsulated PCB panel and the second side of the encapsulated PCB panel.

45 . The method of claim 43 wherein prior to enclosing the PCB panel in the mold cavity, the embedded conductive features are embedded in, and unexposed on the surface of, the printed circuit board panel.

46 . The method of claim 43 , further comprising electrically connecting each of some of the exposed contacts to respective external circuitry configured to provide power or a control signal.

47 . A method of making a plurality of electronic devices each device having a plurality of electrical terminals for establishing electrical connections to the device, comprising:

providing a printed circuit board (PCB) panel including a PCB having a plurality of conductive traces and a plurality of components electrically connected to form a plurality of circuits, the PCB having a plurality of embedded conductive features for making electrical connections to the plurality of circuits, wherein the embedded conductive features are embedded within the PCB and unexposed to an environment outside of the PCB prior to cutting of the PCB;

enclosing the PCB panel, including the PCB, components, and embedded conductive features in a mold cavity;

filling the mold cavity with mold compound;

curing the mold compound to form an encapsulated PCB panel, the embedded conductive features being covered by the cured mold compound on at least one side of the encapsulated PCB panel; and

cutting the encapsulated PCB panel during a singulation process to form at least one edge of each device and to expose at least a portion of the plurality of embedded conductive features and form respective exposed contacts within the at least one edge, wherein the cutting divides the PCB panel producing at least one module having a plurality of layers including respective portions of the PCB panel and the encapsulant on each side of the PCB panel, and the module contains at least one of the circuits, wherein each of some of the exposed contacts in each device is configured to provide a power connection or a control signal connection to a respective circuit within the device.

48 . The method of claim 47 wherein the encapsulated PCB panel includes cured mold compound on a first side of the encapsulated PCB panel and a second side of the encapsulated PCB panel, wherein the embedded conductive features are covered by the cured mold compound on both the first side of the encapsulated PCB panel and the second side of the encapsulated PCB panel.

49 . The method of claim 47 wherein prior to enclosing the PCB panel in the mold cavity, the embedded conductive features are embedded in, and unexposed on the surface of, the printed circuit board panel.

50 . The method of claim 47 , further comprising electrically connecting each of some of the exposed contacts to respective external circuitry configured to provide power or a control signal.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE MERGER TO DELETE 16984527, 16984528 AND 16984529 AND ADD 15186189, 16854984 AND 15941068 PREVIOUSLY RECORDED ON REEL 054135 FRAME 0813. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Nov 16, 2020
From: VLT, INC.
To: VICOR CORPORATION
Reel/Frame 054796/0695 →
MERGER AND CHANGE OF NAME Recorded Oct 22, 2020
From: VLT, INC.; VICOR CORPORATION
To: VICOR CORPORATION
Reel/Frame 054135/0813 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2020
From: VINCIARELLI, PATRIZIO; LAFLEUR, MICHAEL B.; FLEMING, SEAN TIMOTHY; MUTTER, RUDOLPH F.; D'AMICO, ANDREW T.
To: VLT, INC.
Reel/Frame 053002/0665 →
Continuity (4)
Continuation 15186189 · Jun 17, 2016
Division 14116642
Continuation In Part 13105696 · May 11, 2011
Related Publication 20200253060A1 · Aug 6, 2020
References Cited (124)
US 4326765A · Brancaleone · 1982 [cited by applicant]
US 4366342A · Breedlove · 1982 [cited by applicant]
US 4551747A · Gilbert et al. · 1985 [cited by applicant]
US 4711026A · Swiggett et al. · 1987 [cited by applicant]
US 4859807A · Swiggett et al. · 1989 [cited by applicant]
US 5206795A · Belanger, Jr. · 1993 [cited by applicant]
US 5241133A · Mullen et al. · 1993 [cited by applicant]
US 5247423A · Lin · 1993 [cited by examiner]
US 5471366A · Ozawa · 1995 [cited by applicant]
US 5557142A · Gilmore · 1996 [cited by applicant]
US 5728600A · Saxelby, Jr. et al. · 1998 [cited by applicant]
US 5864092A · Gore et al. · 1999 [cited by applicant]
US 5973923A · Jitaru et al. · 1999 [cited by applicant]
US 5987740A · Andrus · 1999 [cited by examiner]
US 5990776A · Jitaru · 1999 [cited by applicant]
US 6001671A · Fjelstad · 1999 [cited by applicant]
US 6028354A · Hoffman · 2000 [cited by applicant]
US 6184585B1 · Martinez et al. · 2001 [cited by applicant]
US 6288905B1 · Chung et al. · 2001 [cited by applicant]
US 6403009B1 · Saxelby, Jr. et al. · 2002 [cited by applicant]
US 6566234B1 · Capote et al. · 2003 [cited by applicant]
US 6586822B1 · Vu · 2003 [cited by applicant]
US 6724083B2 · Ohuchi · 2004 [cited by examiner]
US 6734552B2 · Combs · 2004 [cited by applicant]
US 6830959B2 · Estacio · 2004 [cited by applicant]
US 6930893B2 · Vinciarelli · 2005 [cited by applicant]
US 6940013B2 · Vinciarelli et al. · 2005 [cited by applicant]
US 6982876B1 · Young · 2006 [cited by applicant]
US 7015587B1 · Poddar · 2006 [cited by applicant]
US 7030469B2 · Mahadevan et al. · 2006 [cited by applicant]
US 7049682B1 · Mathews · 2006 [cited by applicant]
US 7190057B2 · Seki · 2007 [cited by applicant]
US 7198987B1 · Warren · 2007 [cited by applicant]
US 7268425B2 · Mallik · 2007 [cited by applicant]
US 7361844B2 · Vinciarelli et al. · 2008 [cited by applicant]
US 7474185B2 · Hooey et al. · 2009 [cited by applicant]
US 7554181B2 · Satou et al. · 2009 [cited by applicant]
US 7646610B2 · Watanabe · 2010 [cited by applicant]
US 7701051B2 · Bayerer et al. · 2010 [cited by applicant]
US 7745259B2 · Sasaki et al. · 2010 [cited by applicant]
US 7772036B2 · Bauer et al. · 2010 [cited by applicant]
US 7786837B2 · Hebert · 2010 [cited by applicant]
US 7952879B1 · Vinciarelli · 2011 [cited by examiner]
US 7972143B2 · Smejtek · 2011 [cited by applicant]
US 7994888B2 · Ikriannikov · 2011 [cited by applicant]
US 8030750B2 · Kim et al. · 2011 [cited by applicant]
US 8138584B2 · Wang · 2012 [cited by applicant]
US 8240035B2 · Nishikawa · 2012 [cited by examiner]
US 8263434B2 · Pagaila · 2012 [cited by applicant]
US 8299882B2 · Ikriannikov · 2012 [cited by applicant]
US 8427269B1 · Vinciarelli · 2013 [cited by applicant]
US 8461672B2 · Haba et al. · 2013 [cited by applicant]
US 8488324B2 · Becker et al. · 2013 [cited by applicant]
US 8513789B2 · Haba et al. · 2013 [cited by applicant]
US 8551815B2 · Avsian et al. · 2013 [cited by applicant]
US 8629543B2 · McElrea et al. · 2014 [cited by applicant]
US 9105613B1 · Chen et al. · 2015 [cited by applicant]
US 9305862B2 · McElrea et al. · 2016 [cited by applicant]
US 9324672B2 · Pagaila · 2016 [cited by applicant]
US 9967984B1 · Vinciarelli · 2018 [cited by applicant]
US 10681821B2 · Karpman · 2020 [cited by applicant]
US 10757816B2 · Vinciarelli · 2020 [cited by examiner]
US 10785871B1 · Vinciarelli et al. · 2020 [cited by applicant]
US 10791645B1 · Vinciarelli · 2020 [cited by applicant]
US 10903734B1 · Vinciarelli · 2021 [cited by applicant]
US 20020053742A1 · Hata · 2002 [cited by examiner]
US 20020096348A1 · Saxelby et al. · 2002 [cited by applicant]
US 20030011054A1 · Jeun et al. · 2003 [cited by applicant]
US 20030030326A1 · Shenai · 2003 [cited by applicant]
US 20040100778A1 · Vinciarelli et al. · 2004 [cited by applicant]
US 20050168960A1 · Asahi et al. · 2005 [cited by applicant]
US 20060097831A1 · Lotfi et al. · 2006 [cited by applicant]
US 20060216867A1 · Kawata et al. · 2006 [cited by applicant]
US 20060272150A1 · Eguchi et al. · 2006 [cited by applicant]
US 20070102142A1 · Reis et al. · 2007 [cited by applicant]
US 20070241440A1 · Hoang et al. · 2007 [cited by applicant]
US 20080036069A1 · Ito · 2008 [cited by examiner]
US 20080145968A1 · Hiew · 2008 [cited by examiner]
US 20090002967A1 · Asami · 2009 [cited by examiner]
US 20090093136A1 · Hiew · 2009 [cited by examiner]
US 20090122578A1 · Beltran · 2009 [cited by applicant]
US 20090160065A1 · Haba et al. · 2009 [cited by applicant]
US 20100013085A1 · Park et al. · 2010 [cited by applicant]
US 20100170085A1 · Schaaf et al. · 2010 [cited by applicant]
US 20100172116A1 · Yorita · 2010 [cited by applicant]
US 20100197150A1 · Smejtek · 2010 [cited by applicant]
US 20100246152A1 · Lin et al. · 2010 [cited by applicant]
US 20100259909A1 · Ho et al. · 2010 [cited by applicant]
US 20100290199A1 · Schmid et al. · 2010 [cited by applicant]
US 20100328913A1 · Kugler et al. · 2010 [cited by applicant]
US 20100330725A1 · Yoshizawa · 2010 [cited by examiner]
US 20110088936A1 · Schaaf et al. · 2011 [cited by applicant]
US 20110248389A1 · Yorita · 2011 [cited by examiner]
US 20120199958A1 · Horibe · 2012 [cited by applicant]
US 20120287582A1 · Vinciarelli et al. · 2012 [cited by applicant]
US 20140124906A1 · Park et al. · 2014 [cited by applicant]
US 20140124907A1 · Park et al. · 2014 [cited by applicant]
US 20140355218A1 · Vinciarelli et al. · 2014 [cited by applicant]
US 20150173258A1 · Chen et al. · 2015 [cited by applicant]
US 20150181719A1 · Vinciarelli et al. · 2015 [cited by applicant]
US 20150181727A1 · Vinciarelli · 2015 [cited by applicant]
US 20160302312A1 · Vinciarelli et al. · 2016 [cited by applicant]
US 20170011982A1 · Theuss et al. · 2017 [cited by applicant]
US 20170048981A1 · Hu et al. · 2017 [cited by applicant]
US 20190059152A1 · Boozer et al. · 2019 [cited by applicant]
US 20190116667A1 · Chen et al. · 2019 [cited by applicant]
WO WO1995027308 · 1995 [cited by applicant]
WO WO2004017399 · 2004 [cited by applicant]
AFM Microelectronics Inc., “General Purpose Capacitors,” www.afmmicroelectronics.com, 14 pages, published on or before Jul. 26, 2010. [cited by applicant]
International Search Report and Written Opinion, PCT/US2012/37495, May 6, 2013, 18 pages. [cited by applicant]
Kahn, “Technical Information: Multilayer Ceramic Capacitors—Materials and Manufacture,” Microelectronics Inc., 8 pages, published on or before Jul. 26, 2010. [cited by applicant]
Reply to Action in U.S. Appl. No. 13/105,696, dated Mar. 25, 2014, 10 pages. [cited by applicant]
Reply to Action in U.S. Appl. No. 14/116,642, dated May 9, 2016, 16 pages. [cited by applicant]
Reply to Action in U.S. Appl. No. 14/635,420, dated Nov. 13, 2015, 9 pages. [cited by applicant]
Reply to Ex Parte Quayle Action in U.S. Appl. No. 14/635,467, dated May 6, 2016, 5 pages. [cited by applicant]
U.S. Appl. No. 12/493,773, entitled “Encapsulation Method and Apparatus for Electronic Modules”, Application and Preliminary Amendment filed Jun. 29, 2009, 63 pages. [cited by applicant]
USPTO Ex Parte Quayle Office Action in U.S. Appl. No. 14/635,467, dated Mar. 11, 2016, 5 pages. [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 13/105,696, dated Nov. 18, 2014, 6 pages. [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 14/116,642, dated Jun. Examiner Shrestha. [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 14/635,420, dated Feb. 17, 2016, 6 pages. [cited by applicant]
USPTO Office Action in U.S. Appl. No. 13/105,696, dated Sep. 25, 2013, 8 pages. [cited by applicant]
USPTO Office Action in U.S. Appl. No. 14/116,642, dated Feb. 9, 2016, 15 pages. [cited by applicant]
USPTO Office Action in U.S. Appl. No. 14/635,420, dated Oct. 22, 2015, 6 pages. [cited by applicant]
USPTO Supplemental Notice of Allowance in U.S. Appl. No. 14/635,420, dated Apr. 27, 2016, 6 pages. [cited by applicant]